[Paper Review] CVC4 at the SMT Competition 2018

Clark Barrett, Haniel Barbosa+9 more|arXiv (Cornell University)|Jun 20, 2018

Formal Methods in Verification3 references3 citations

TL;DR

This paper presents the CVC4 SMT solver's configuration for the 2018 SMT Competition, highlighting key enhancements including a native floating-point solver using SymFPU and lazy bit-vector handling, adoption of CaDiCaL as the SAT back-end for eager bit-blasting, improved non-linear arithmetic heuristics, default symbolic inverse-based quantified bit-vector solving, and experimental support for strings via bounded model-finding and context-dependent simplification. These advances enabled CVC4 to compete across all main, application, and unsat core tracks, as well as the QF_SLIA experimental division.

ABSTRACT

This paper is a description of the CVC4 SMT solver as entered into the 2018 SMT Competition. We only list important differences from the 2017 SMT Competition version of CVC4. For further and more detailed information about CVC4, please refer to the original paper, the CVC4 website, or the source code on GitHub.

Motivation & Objective

• To enhance CVC4’s support for floating-point logics, enabling participation in all FP logic tracks of the SMT Competition 2018.
• To improve performance and scalability in bit-vector and non-linear arithmetic solving through updated SAT back-ends and heuristic techniques.
• To introduce a novel symbolic inverse-based approach for solving quantified bit-vector formulas as the default strategy.
• To extend CVC4’s capabilities to handle string logic in the QF_SLIA experimental division using bounded model-finding and context-sensitive simplification.
• To optimize CVC4 configurations across multiple competition tracks—main, application, unsat core, and experimental—using tailored compilation and parameter settings.

Proposed method

• CVC4’s floating-point solver translates floating-point operations into bit-vector operations using SymFPU, which are then processed by the lazy bit-vector engine.
• The eager bit-blasting engine now uses CaDiCaL (commit b44ce4f) as the SAT back-end, replacing CryptoMiniSat 4, improving performance on bit-vector problems.
• Non-linear arithmetic is handled via heuristics inspired by Cimatti et al., with fallback to bit-vector encoding when needed, using CaDiCaL as the underlying SAT solver.
• For quantified bit-vectors, CVC4 employs a symbolic inverse computation method for bit-vector operators, now the default solving strategy.
• String solving in QF_SLIA uses a finite model-finding approach with bounded string length and context-dependent simplification for extended string functions like contains and replace.
• Configurations are tailored per track: CVC4-main for non-interactive inputs without proof, CVC4-application for interactive inputs, CVC4-uc for proof-enabled unsat core extraction, and CVC4-experimental-idl-2 for incremental shortest-path solving in IDL.

Experimental results

Research questions

• RQ1 How can CVC4 be extended to natively support floating-point logics across all competition tracks?
• RQ2 What impact does switching from CryptoMiniSat 4 to CaDiCaL as the SAT back-end have on performance in eager bit-blasting?
• RQ3 Can symbolic inverse computation improve the efficiency and correctness of quantified bit-vector solving?
• RQ4 How effective is a bounded finite model-finding approach combined with context-dependent simplification for solving string logic problems?
• RQ5 What configuration strategies maximize CVC4’s performance across diverse SMT Competition tracks, including main, application, unsat core, and experimental divisions?

Key findings

• CVC4 successfully entered all divisions of the main, application, and unsat core tracks in the 2018 SMT Competition, demonstrating broad support for diverse logical theories.
• The integration of a floating-point solver via SymFPU enabled CVC4 to compete in all FP logic tracks for the first time.
• Adoption of CaDiCaL as the SAT back-end for eager bit-blasting significantly improved performance over the previous CryptoMiniSat 4 configuration.
• The symbolic inverse-based method for quantified bit-vectors became the default strategy, improving handling of complex bit-vector quantifier problems.
• The experimental QF_SLIA configuration successfully applied bounded model-finding and context-sensitive simplification to support extended string operations in the competition.
• Tailored configurations for each track—using different compilation options and parameters—enabled optimal performance across interactive, non-interactive, and proof-producing use cases.