[Paper Review] DCSYNTH: Guided Reactive Synthesis with Soft Requirements for Robust Controller and Shield Synthesis

Amol Wakankar, Paritosh K. Pandya+1 more|arXiv (Cornell University)|Nov 6, 2017

Formal Methods in Verification7 references3 citations

TL;DR

DCSYNTH is a reactive synthesis tool that generates high-quality controllers using discrete duration calculus (QDDC) with hard and soft requirements. It enables guided synthesis by prioritizing soft requirements (e.g., minimizing latency, improving robustness) while ensuring hard safety and liveness constraints are always met, resulting in compact, robust controllers and runtime shields that tolerate burst errors.

ABSTRACT

DCSYNTH is a tool for the synthesis of controllers from safety and bounded liveness requirements given in interval temporal logic QDDC. It investigates the role of soft requirements (with priorities) in obtaining high quality controllers. A QDDC formula specifies past time properties. In DCSYNTH synthesis, hard requirements must be invariantly satisfied whereas soft requirements may be satisfied "as much as possible" in a best effort manner by the controller. Soft requirements provide an invaluable ability to guide the controller synthesis. In the paper, using DCSYNTH, we show the application of soft requirements in obtaining robust controllers with various specifiable notions of robustness. We also show the use of soft requirements to specify and synthesize efficient runtime enforcement shields which can correct burst errors. Finally, we discuss the use of soft requirements in improving the latency of controlled system.

Motivation & Objective

• To address the lack of guidance in reactive synthesis tools, which often produce multiple correct but suboptimal controllers.
• To improve controller quality beyond correctness-by-construction by incorporating soft requirements with priorities.
• To enable synthesis of robust controllers that maintain guarantees under environmental assumption violations.
• To support automatic synthesis of compact, efficient runtime enforcement shields that correct burst errors.
• To reduce controller latency through soft requirement-driven optimization.

Proposed method

• Uses interval temporal logic QDDC to specify both hard safety/liveness properties and soft requirements with priority weights.
• Applies a locally optimal synthesis strategy that selects outputs satisfying maximal subsets of soft requirements while strictly enforcing hard constraints.
• Integrates symbolic model checking techniques to measure worst-case latency using path-finding algorithms.
• Supports shield synthesis by specifying the shield as a controller that corrects erroneous outputs while minimizing deviation.
• Employs a two-phase synthesis: first, a controller is synthesized from hard and soft requirements; second, a shield is synthesized to enforce correctness under transient failures.
• Uses a formal specification language within DCSYNTH to define system interfaces, assumptions, requirements, and soft goals with weighted priorities.

Experimental results

Research questions

• RQ1 Can soft requirements with priorities guide reactive synthesis to produce higher-quality controllers beyond correctness?
• RQ2 How can soft requirements be used to synthesize controllers with specific robustness properties such as 'never-give-up' or 'don't-be-lazy'?
• RQ3 Can soft requirements enable the synthesis of compact, efficient runtime shields that correct burst errors?
• RQ4 To what extent do soft requirements reduce controller latency in real-time systems?
• RQ5 Can the same specification framework support both controller and shield synthesis with unified formalism?

Key findings

• DCSYNTH successfully synthesizes robust controllers that satisfy 'never-give-up' and 'don't-be-lazy' robustness criteria by encoding them as soft requirements with appropriate priorities.
• The tool generates compact runtime enforcement shields capable of correcting burst errors, outperforming prior work in shield size and efficiency.
• Soft requirement-driven synthesis reduces worst-case latency in controlled systems, as validated through symbolic path analysis using the CTLDC tool.
• The framework supports the automatic synthesis of both controllers and shields from a unified QDDC specification, reducing engineering effort.
• Experimental results on the mine pump and 4-cell arbiter case studies confirm that DCSYNTH produces controllers that satisfy hard constraints while maximizing satisfaction of soft goals in a locally optimal manner.
• The tool demonstrates scalability and practicality for real-world embedded control and runtime enforcement applications.