[Paper Review] DeFT: A Deadlock-Free and Fault-Tolerant Routing Algorithm for 2.5D Chiplet Networks

Ebadollah Taheri, Sudeep Pasricha+1 more|arXiv (Cornell University)|Dec 16, 2021

Interconnection Networks and Systems4 citations

TL;DR

This paper proposes DeFT, the first deadlock-free and fault-tolerant routing algorithm for 2.5D chiplet networks, which ensures deadlock freedom via virtual network (VN) assignment and enables dynamic, traffic-aware vertical link (VL) selection to tolerate up to 25% VL faults. DeFT achieves 100% network reachability under fault scenarios and reduces latency by up to 40% with less than 2% area overhead compared to state-of-the-art methods.

ABSTRACT

By interconnecting smaller chiplets through an interposer, 2.5D integration offers a cost-effective and high-yield solution to implement large-scale modular systems. Nevertheless, the underlying network is prone to deadlock, despite deadlock-free chiplets, and to different faults on the vertical links used for connecting the chiplets to the interposer. Unfortunately, existing fault-tolerant routing techniques proposed for 2D and 3D on-chip networks cannot be applied to chiplet networks. To address these problems, this paper presents the first deadlock-free and fault-tolerant routing algorithm, called DeFT, for 2.5D integrated chiplet systems. DeFT improves the redundancy in vertical-link selection to tolerate faults in vertical links while considering network congestion. Moreover, DeFT can tolerate different vertical-link-fault scenarios while accounting for vertical-link utilization. Compared to the state-of-the-art routing algorithms in 2.5D chiplet systems, our simulation results show that DeFT improves network reachability by up to 75% with a fault rate of up to 25% and reduces the network latency by up to 40% for multi-application execution scenarios with less than 2% area overhead.

Motivation & Objective

• To address the lack of deadlock-free and fault-tolerant routing in 2.5D chiplet networks, which are prone to cyclic dependencies and vertical-link (VL) faults.
• To overcome the limitations of existing 2D and 3D network fault-tolerance techniques, which are inapplicable to the irregular, multi-chiplet 2.5D topology.
• To enable full path redundancy and dynamic VL selection that improves fault tolerance and load balancing under varying traffic and fault conditions.
• To maintain deadlock freedom while maximizing routing flexibility and minimizing hardware overhead in modular chiplet systems.
• To achieve high network reliability and low latency in multi-application, real-world traffic scenarios with minimal area cost.

Proposed method

• DeFT employs a novel virtual network (VN) assignment strategy to balance virtual channel (VC) utilization and guarantee deadlock freedom, even with unrestricted VL selection.
• It introduces a dynamic, traffic-aware vertical link selection mechanism that prioritizes underutilized and fault-tolerant VLs to reduce congestion and improve fault resilience.
• The algorithm uses a fault-tolerant look-up table to maintain routing state and enable path reconfiguration in response to VL failures.
• It supports full reachability by allowing any VL to be used for routing, even when up to 25% of VLs are faulty, by avoiding restrictive turn models.
• The design integrates minimal hardware logic for VN assignment and fault-aware VL selection, adding less than 2% area overhead.
• DeFT is evaluated using real application workloads and fault injection models across 4- and 6-chiplet systems under varying traffic loads.

Experimental results

Research questions

• RQ1 Can a routing algorithm achieve deadlock freedom in 2.5D chiplet networks without restricting vertical link (VL) selection?
• RQ2 How can fault tolerance be achieved in 2.5D chiplet networks under arbitrary VL fault patterns, especially when traditional 2D/3D techniques fail?
• RQ3 To what extent can dynamic, traffic-aware VL selection reduce network latency and improve load balancing under high fault and traffic rates?
• RQ4 What is the hardware and power overhead of integrating fault-tolerant and deadlock-free routing in 2.5D chiplet systems?
• RQ5 How does DeFT compare to state-of-the-art algorithms like MTR and RC in terms of reachability and latency under realistic fault and traffic conditions?

Key findings

• DeFT achieves 100% network reachability under 25% vertical-link fault rates, significantly outperforming MTR (≤3.1% fault tolerance for 4-chiplet systems) and RC (no fault tolerance).
• In multi-application scenarios, DeFT reduces network latency by up to 40% compared to MTR and RC, especially under high traffic loads.
• Under 25% fault rates, DeFT improves worst-case reachability by up to 75% compared to MTR and 50% compared to RC.
• The algorithm maintains low hardware overhead, adding less than 2% area and 1% power overhead compared to MTR and RC.
• DeFT with dynamic VL selection reduces latency more effectively than distance-based or random VL selection strategies, particularly under high fault rates.
• The proposed dynamic VL selection strategy outperforms static or random selection by balancing load and minimizing congestion in fault-prone environments.