[Paper Review] Equivalence Checking and Simulation By Computing Range Reduction

Eugene Goldberg|arXiv (Cornell University)|Jul 8, 2015

Formal Methods in Verification7 references4 citations

TL;DR

This paper introduces a novel approach to equivalence checking and simulation in digital circuit verification using Computing Range Reduction (CRR), which efficiently identifies outputs that disappear from a circuit's range when certain inputs are excluded. By leveraging partial quantifier elimination, CRR enables scalable, proof-like verification that outperforms traditional methods in both circuit size and structural dissimilarity, offering a hybrid advantage over existing equivalence checkers.

ABSTRACT

We introduce new methods of equivalence checking and simulation based on Computing Range Reduction (CRR). Given a combinational circuit $N$, the CRR problem is to compute the set of outputs that disappear from the range of $N$ if a set of inputs of $N$ is excluded from consideration. Importantly, in many cases, range reduction can be efficiently found even if computing the entire range of $N$ is infeasible. Solving equivalence checking by CRR facilitates generation of proofs of equivalence that mimic a "cut propagation" approach. A limited version of such an approach has been successfully used by commercial tools. Functional verification of a circuit $N$ by simulation can be viewed as a way to reduce the complexity of computing the range of $N$. Instead of finding the entire range of $N$ and checking if it contains a bad output, such a range is computed only for one input. Simulation by CRR offers an alternative way of coping with the complexity of range computation. The idea is to exclude a subset of inputs of $N$ and compute the range reduction caused by such an exclusion. If the set of disappeared outputs contains a bad one, then $N$ is buggy.

Motivation & Objective

• To address the scalability limitations of traditional equivalence checking and simulation methods in large or dissimilar circuits.
• To develop a new verification paradigm based on range reduction that avoids full range computation.
• To enable efficient, proof-like verification by mimicking 'cut propagation' strategies used in industrial tools.
• To demonstrate that CRR-based methods outperform both structural similarity-based and general-purpose equivalence checkers in diverse circuit scenarios.

Proposed method

• The CRR problem is formulated as identifying outputs that vanish from a circuit’s range when a subset of input assignments is excluded.
• Equivalence checking is reduced to checking whether specific output pairs (e.g., (0,1) and (1,0)) disappear from the range of a composed two-output circuit.
• Simulation-by-exclusion computes the set of outputs that disappear due to input exclusion, enabling early detection of bugs without full range analysis.
• The method uses partial quantifier elimination (PQE) to efficiently compute range reduction, avoiding the intractability of full range computation.
• An iterative algorithm incrementally adds constraints to exclude inputs and checks for disappearing outputs, with periodic simulation runs to improve counterexample discovery.
• A threshold-based mechanism triggers regular simulation when too many constraints are added, enhancing search efficiency.

Experimental results

Research questions

• RQ1 Can range reduction be used to efficiently verify circuit equivalence without computing the full output range?
• RQ2 How does CRR-based equivalence checking compare to traditional BDD- or SAT-based methods in terms of scalability and structural sensitivity?
• RQ3 Can simulation-by-exclusion detect buggy behavior earlier than standard simulation by focusing on output disappearance?
• RQ4 To what extent can partial quantifier elimination support efficient CRR computation in practice?
• RQ5 Does the CRR approach naturally support proof generation that mirrors industrial 'cut propagation' techniques?

Key findings

• CRR enables equivalence checking by detecting the disappearance of specific output pairs when inputs are constrained, providing a scalable alternative to full range computation.
• The method supports 'cut advancement' strategies that are effective in industrial verification, offering a formal basis for such heuristics.
• Simulation-by-exclusion can detect buggy behavior by identifying whether a bad output disappears under input exclusion, allowing early termination if the output remains.
• Partial quantifier elimination (PQE) provides an efficient computational foundation for CRR, avoiding the need to compute the entire output range.
• The approach outperforms general-purpose equivalence checkers on large circuits and structural similarity-based tools on dissimilar circuits, combining the strengths of both paradigms.
• Periodic simulation calls within the CRR framework improve counterexample discovery by reducing the search space while maintaining efficiency.