[Paper Review] Evaluation of silicon consumption for a connectionless Network-on-Chip

Marcelo Daniel Berejuck, Antônio Augusto Fröhlich|arXiv (Cornell University)|Nov 13, 2014

Interconnection Networks and Systems18 references3 citations

TL;DR

This paper proposes a connectionless Network-on-Chip (NoC) architecture that enables variable-bit-rate multimedia traffic by embedding routing information in each flit, allowing dynamic interleaving of multiple flows without dedicated connections. The approach achieves lower average latency than resource-reserved networks under high load (80%) and demonstrates favorable silicon area efficiency in both FPGA and ASIC implementations, with detailed evaluation of area and power trade-offs.

ABSTRACT

We present the design and evaluation of a predictable Network-on-Chip (NoC) to interconnect processing units running multimedia applications with variable-bit-rate. The design is based on a connectionless strategy in which flits from different communication flows are interleaved in the same communication channel between routers. Each flit carries routing information used by routers to perform arbitration and scheduling of the corresponding output communication channel. Analytic comparisons show that our approach keeps average latency lower than a network based on resource reservation, when both networks are working over 80% of offered load. We also evaluate the proposed NoC on FPGA and ASIC technologies to understand the trade-off due to our approach, in terms of silicon consumption.

Motivation & Objective

• To design a predictable, connectionless NoC for interconnecting processing units running variable-bit-rate multimedia applications.
• To reduce latency under high network load compared to traditional resource-reserved NoC approaches.
• To evaluate silicon area and power consumption trade-offs in both FPGA and ASIC technologies.
• To enable efficient hardware utilization by eliminating connection setup overhead and supporting dynamic flow multiplexing.

Proposed method

• The NoC uses a flit-based communication model where each flit contains embedded routing information for dynamic channel arbitration and scheduling.
• Routers perform output channel selection based on the routing header in each flit, eliminating the need for connection setup or virtual circuits.
• The architecture supports interleaving of multiple communication flows over shared physical channels, improving link utilization.
• Analytical models compare average latency between connectionless and resource-reserved NoC under varying load conditions.
• FPGA and ASIC implementations are used to evaluate silicon area, latency, and power consumption.
• The evaluation includes comparative analysis of area overhead and performance under 80% offered load.

Experimental results

Research questions

• RQ1 How does a connectionless NoC perform in terms of average latency compared to a resource-reserved NoC under high network load (80%)?
• RQ2 What is the silicon area consumption of a connectionless NoC in FPGA and ASIC technologies?
• RQ3 How does embedding routing information in flits affect hardware complexity and resource utilization?
• RQ4 Can a connectionless NoC maintain predictable performance for variable-bit-rate multimedia traffic?
• RQ5 What is the trade-off between latency, area, and power efficiency in the proposed NoC design?

Key findings

• The connectionless NoC achieves lower average latency than a resource-reserved NoC when both operate at 80% offered load.
• The proposed NoC demonstrates favorable silicon area consumption, with detailed area breakdown reported for FPGA and ASIC realizations.
• The absence of connection setup and virtual channels reduces hardware complexity and improves resource utilization.
• The design maintains predictable performance for variable-bit-rate multimedia workloads due to per-flit routing decisions.
• The FPGA and ASIC evaluations confirm that the connectionless approach offers a viable trade-off between performance and silicon area.