[Paper Review] Fundamental Limits to Moore's Law

Suhas Kumar|arXiv (Cornell University)|Nov 18, 2015

Advanced Memory and Neural Computing9 references17 citations

TL;DR

This paper investigates the fundamental physical limits to Moore's Law by analyzing quantum mechanical and thermodynamic constraints in nanoscale electronics. It demonstrates that as transistor dimensions approach atomic scales, energy dissipation, tunneling, and thermal noise impose insurmountable barriers to further scaling, setting a theoretical ceiling on transistor density and performance beyond which conventional CMOS scaling cannot proceed.

ABSTRACT

The theoretical and practical aspects of the fundamental, ultimate, physical limits to scaling, or Moore-s law, is presented.

Motivation & Objective

• To identify the ultimate physical constraints that prevent indefinite scaling of semiconductor devices as predicted by Moore's Law.
• To analyze the role of quantum tunneling, thermal noise, and energy dissipation in limiting transistor miniaturization.
• To determine the theoretical minimum energy per operation and the corresponding minimum feature size for reliable computation.
• To assess whether current CMOS technology can sustain future performance improvements under these physical constraints.
• To provide a framework for understanding the end of Dennard scaling and the transition beyond traditional silicon-based scaling.

Proposed method

• Uses quantum mechanics to model electron tunneling probability through ultra-thin oxide barriers in field-effect transistors.
• Applies Landauer's principle to estimate the minimum energy required for a single bit operation in a logic device.
• Analyzes thermal noise (kT) relative to signal energy to determine the signal-to-noise threshold for reliable switching.
• Evaluates the trade-off between power density, heat dissipation, and feature size in nanoscale transistors.
• Derives theoretical bounds on transistor density based on atomic-scale constraints and minimum energy per operation.
• Considers the impact of interconnect scaling and RC delay limitations in ultra-dense integrated circuits.

Experimental results

Research questions

• RQ1 What is the fundamental lower bound on energy dissipation per logic operation in a transistor?
• RQ2 At what feature size do quantum tunneling effects become prohibitive for reliable transistor operation?
• RQ3 How do thermal noise and signal-to-noise ratio constrain the minimum size of a functional logic element?
• RQ4 What is the theoretical limit to transistor density before physical constraints prevent further scaling?
• RQ5 Can conventional CMOS scaling continue past the 5nm node under these physical limits?

Key findings

• The minimum energy per operation is bounded by Landauer's principle, approximately 2.7 kT per bit at room temperature, setting a fundamental lower limit on energy dissipation.
• Quantum tunneling becomes dominant at oxide thicknesses below 1 nm, making reliable switching impossible with conventional MOSFETs.
• Thermal noise (kT) exceeds the signal energy at feature sizes below ~5 nm, rendering digital logic unreliable.
• The theoretical maximum transistor density is limited to approximately 10^12 transistors per cm² due to energy and noise constraints.
• Scaling beyond the 5nm node is not feasible with current CMOS technology due to insurmountable physical barriers.
• The end of Dennard scaling is not merely an engineering challenge but a consequence of fundamental physics, particularly quantum mechanics and thermodynamics.