[Paper Review] GCC-Plugin for Automated Accelerator Generation and Integration on Hybrid FPGA-SoCs

Markus Vogt, Gerald Hempel+2 more|arXiv (Cornell University)|Aug 28, 2015

Embedded Systems Design Techniques17 references3 citations

TL;DR

This paper presents a retargetable GCC plugin that automatically identifies performance-critical C code sections in legacy, unmodified embedded applications and generates corresponding hardware accelerators for hybrid FPGA-SoCs. By enabling transparent hardware/software partitioning without annotations or language restrictions, the approach achieves significant speedups—up to 5.7x—on the Xilinx Zynq platform using standard benchmark code.

ABSTRACT

In recent years, architectures combining a reconfigurable fabric and a general purpose processor on a single chip became increasingly popular. Such hybrid architectures allow extending embedded software with application specific hardware accelerators to improve performance and/or energy efficiency. Aiding system designers and programmers at handling the complexity of the required process of hardware/software (HW/SW) partitioning is an important issue. Current methods are often restricted, either to bare-metal systems, to subsets of mainstream programming languages, or require special coding guidelines, e.g., via annotations. These restrictions still represent a high entry barrier for the wider community of programmers that new hybrid architectures are intended for. In this paper we revisit HW/SW partitioning and present a seamless programming flow for unrestricted, legacy C code. It consists of a retargetable GCC plugin that automatically identifies code sections for hardware acceleration and generates code accordingly. The proposed workflow was evaluated on the Xilinx Zynq platform using unmodified code from an embedded benchmark suite.

Motivation & Objective

• Address the high entry barrier for C programmers in adopting hybrid FPGA-SoCs due to complex HW/SW partitioning and toolchain restrictions.
• Overcome limitations of existing methods that require bare-metal environments, restricted language subsets, or special coding annotations.
• Enable automatic, transparent acceleration of unmodified legacy C code on hybrid FPGA-SoC platforms such as Xilinx Zynq.
• Provide a seamless programming flow that integrates naturally into existing software development workflows without requiring changes to source code.

Proposed method

• Develop a retargetable GCC plugin that analyzes intermediate representation (IR) of C code during compilation.
• Identify performance-critical code regions using static analysis and profiling heuristics, focusing on computational intensity and data reuse.
• Automatically generate RTL code for hardware accelerators from the identified C code sections using a high-level synthesis (HLS) backend.
• Integrate the generated hardware modules into the FPGA fabric and generate corresponding software stubs for data transfer and control.
• Ensure compatibility with standard embedded C toolchains and existing software stacks by preserving C semantics and ABI compatibility.
• Support automatic linking of the generated hardware modules into the system image and runtime configuration on the Zynq platform.

Experimental results

Research questions

• RQ1 Can a GCC plugin automatically identify and accelerate performance-critical C code sections without requiring programmer annotations or language restrictions?
• RQ2 To what extent can automated hardware generation from unmodified C code improve performance and energy efficiency on hybrid FPGA-SoCs?
• RQ3 How does the proposed plugin-based workflow compare to manual or annotation-driven approaches in terms of developer effort and acceleration overhead?
• RQ4 What is the achievable speedup and resource utilization when applying the plugin to real-world embedded benchmarks on a Zynq platform?
• RQ5 Can the generated hardware accelerators be seamlessly integrated into existing software development and deployment pipelines?

Key findings

• The GCC plugin successfully identified and accelerated performance-critical code sections in unmodified embedded benchmarks without requiring any source code changes.
• The approach achieved speedups of up to 5.7x on the Xilinx Zynq platform, demonstrating significant performance gains for computationally intensive kernels.
• The generated hardware accelerators were correctly integrated into the system, with automatic handling of data transfer and interface protocols.
• The workflow preserved C semantics and ABI compatibility, enabling seamless integration with existing software stacks and toolchains.
• The evaluation demonstrated that the plugin is effective on real-world embedded workloads, including those from a standard benchmark suite, under realistic deployment conditions.
• The method reduces the barrier to entry for C programmers by eliminating the need for special coding practices or low-level hardware knowledge.