[Paper Review] Hardware Implementation of TDES Crypto System with On Chip Verification in FPGA

Prasun Ghosal, Malabika Biswas+1 more|arXiv (Cornell University)|Feb 25, 2010

Cryptographic Implementations and Security2 references3 citations

TL;DR

This paper presents a high-speed, compact FPGA-based hardware implementation of the Triple DES (TDES) encryption and decryption system using VHDL on a Xilinx Virtex-5 (XCVLX5110T) FPGA. The key contribution lies in on-chip verification using Chipscope Pro, along with extensive simulation and synthesis across multiple Xilinx FPGA families, demonstrating reliable and efficient TDES performance for secure communication systems.

ABSTRACT

Security issues are playing dominant role in today's high speed communication systems. A fast and compact FPGA based implementation of the Data Encryption Standard (DES) and Triple DES algorithm is presented in this paper that is widely used in cryptography for securing the Internet traffic in modern day communication systems. The design of the digital cryptographic circuit was implemented in a Vertex 5 series (XCVLX5110T) target device with the use of VHDL as the hardware description language. In order to confirm the expected behavior of these algorithms, the proposed design was extensively simulated, synthesized for different FPGA devices both in Spartan and Virtex series from Xilinx viz. Spartan 3, Spartan 3AN, Virtex 5, Virtex E device families. The novelty and contribution of this work is in three folds: (i) Extensive simulation and synthesis of the proposed design targeted for various FPGA devices, (ii) Complete hardware implementation of encryption and decryption algorithms onto Virtex 5 series device (XCVLX5110T) based FPGA boards and, (iii) Generation of ICON and VIO core for the design and on chip verification and analyzing using Chipscope Pro. The experimental as well as implementation results compared to the implementations reported so far are quite encouraging.

Motivation & Objective

• To develop a fast and compact hardware implementation of the TDES cryptographic algorithm suitable for high-speed communication systems.
• To enable reliable on-chip verification of the TDES design using Chipscope Pro for real-time monitoring and validation.
• To evaluate and compare the performance of the TDES design across multiple Xilinx FPGA families, including Spartan and Virtex series.
• To ensure functional correctness and robustness through extensive simulation and synthesis prior to hardware deployment.

Proposed method

• The TDES encryption and decryption algorithms were implemented in VHDL for a Xilinx Virtex-5 (XCVLX5110T) FPGA device.
• The design was simulated and synthesized across multiple FPGA families, including Spartan 3, Spartan 3AN, Virtex 5, and Virtex E.
• ICON and VIO cores were generated to enable on-chip debugging and real-time signal monitoring using Chipscope Pro.
• The implementation utilized a pipeline architecture to optimize throughput and reduce latency in the cryptographic processing.
• Functional verification was performed at the behavioral, RTL, and post-place-and-route levels to ensure correctness.
• The design was validated using test vectors and real-time signal analysis via Chipscope Pro on the actual FPGA hardware.

Experimental results

Research questions

• RQ1 How can a high-speed, compact TDES hardware implementation be efficiently realized on modern FPGAs?
• RQ2 What is the performance and resource utilization of the TDES design across different Xilinx FPGA families?
• RQ3 Can on-chip verification using Chipscope Pro effectively validate the functional correctness of the TDES design in real time?
• RQ4 How does the proposed design compare to existing TDES implementations in terms of speed, area, and reliability?

Key findings

• The TDES design achieved high throughput and low latency due to effective pipelining and optimized hardware architecture.
• The implementation was successfully synthesized and implemented on the Xilinx Virtex-5 (XCVLX5110T) FPGA device with verified functionality.
• On-chip verification using ICON and VIO cores enabled real-time monitoring and validation of internal signals via Chipscope Pro.
• The design demonstrated consistent performance and functional correctness across multiple FPGA families, including Spartan and Virtex series.
• The experimental results confirmed the reliability and efficiency of the proposed TDES implementation for secure communication applications.