[Paper Review] Hardware Software Co-design for Automotive CPS using Architecture Analysis and Design Language

Yuchen Zhou, John S. Baras+1 more|arXiv (Cornell University)|Mar 16, 2016

Real-Time Systems Scheduling5 references3 citations

TL;DR

This paper proposes a hardware-software co-design methodology for automotive cyber-physical systems using Architecture Analysis and Design Language (AADL) to enable early, integrated analysis of system architecture. By modeling both hardware and software components in AADL and performing real-time simulation and schedulability analysis, the method supports systematic verification and optimization of control system performance, with results showing that 80ms sampling is optimal for single-core ACC systems and 40ms for dual-core configurations.

ABSTRACT

Modern cyber-physical systems (CPS) have a close inter-dependence between software and physical components. Automotive embedded systems are typical CPS, as physical chips, sensors and actuators are physical components and software embedded within are the cyber components. The current stage of embedded systems is highly complex in architecture design for both software and hardware. It is common in industrial practice that high level control algorithm development and low level code implementation on hardware platforms are developed separately with limited shared information. However, software code and hardware architecture become closely related with the increasing complexity. Correlated requirements and dependencies between hardware and software are emerging problems of industrial practice. We demonstrate in this paper a method to link model based system design with real-time simulations and analysis of the architecture model. This allows hardware software co-design and thus early selection of hardware architecture.

Motivation & Objective

• Address the challenge of fragmented development between high-level control algorithms and low-level hardware implementation in automotive embedded systems.
• Reduce over-design and high system costs by enabling early, integrated analysis of hardware and software architecture.
• Improve system integrity and reduce integration costs through a unified modeling and analysis framework.
• Support model-based development with formal analysis of timing, schedulability, and performance constraints in real-time simulations.
• Enable systematic requirement refinement and architecture selection before implementation through a standardized modeling language.

Proposed method

• Model the entire automotive control system, including hardware platforms, software components, and communication protocols, using the Architecture Analysis and Design Language (AADL).
• Define software partitions and system-level properties such as execution times, memory footprint, and I/O delays within the AADL model.
• Perform schedulability analysis using Cheddar to evaluate real-time feasibility of different sampling periods (20ms, 40ms, 80ms, 160ms).
• Conduct real-time simulations using Truetime to evaluate controller performance and data synchronization under various timing conditions.
• Validate system behavior under fault scenarios, such as oversampling and downsampling, to assess robustness and timing resilience.
• Use the same AADL model for both high-level architectural analysis and detailed implementation-level simulation, ensuring consistency across design phases.

Experimental results

Research questions

• RQ1 How can hardware and software architecture be co-designed early in the development lifecycle to improve system integration and reduce cost?
• RQ2 What is the optimal sampling period for an adaptive cruise control (ACC) system on single-core and dual-core processors while meeting real-time and safety constraints?
• RQ3 How does timing variation (e.g., oversampling or downsampling) affect controller performance and schedulability in embedded automotive systems?
• RQ4 To what extent can AADL-based modeling enable consistent verification and validation across different abstraction levels?
• RQ5 Can real-time simulation and schedulability analysis in the same AADL framework improve system robustness and reduce over-design?

Key findings

• For a single-core implementation, 80ms sampling provides the best balance between performance degradation and schedulability, with tolerable controller degradation despite some missed deadlines.
• In the dual-core configuration, 40ms sampling achieves optimal performance and schedulability, with threads properly synchronized across ECUs and no deadline misses.
• The 20ms sampling rate caused abnormal system behavior and scheduler overload in the dual-core setup, confirming the results of schedulability analysis.
• The 160ms sampling rate produced results similar to 80ms, indicating that performance remains acceptable but less responsive than 40ms or 80ms.
• The single-core system with 80ms sampling achieved comparable headway performance to the dual-core system with 40ms sampling, but with lower implementation complexity and cost.
• The AADL-based method enabled consistent, early verification of both architectural constraints and real-time controller behavior using a unified model.