[Paper Review] Hier-RTLMP: A Hierarchical Automatic Macro Placer for Large-scale Complex IP Blocks

Andrew B. Kahng, Ravi Varadarajan+1 more|arXiv (Cornell University)|Apr 23, 2023

Embedded Systems Design Techniques4 citations

TL;DR

Hier-RTLMP is a hierarchical macro placer that automatically generates high-quality floorplans for large-scale RTL designs with hundreds of macros by transforming logical hierarchy into a multilevel physical hierarchy, enabling core-area macro tiling while preserving dataflow and power grid efficiency. It achieves 13× faster runtime than RTL-MP and outperforms both RTL-MP and a leading commercial tool in post-route timing and wirelength metrics.

ABSTRACT

In a typical RTL to GDSII flow, floorplanning or macro placement is a critical step in achieving decent quality of results (QoR). Moreover, in today's physical synthesis flows (e.g., Synopsys Fusion Compiler or Cadence Genus iSpatial), a floorplan .def with macro and IO pin placements is typically needed as an input to the front-end physical synthesis. Recently, with the increasing complexity of IP blocks, and in particular with auto-generated RTL for machine learning (ML) accelerators, the number of hard macros in a single RTL block can easily run into the several hundreds. This makes the task of generating an automatic floorplan (.def) with IO pin and macro placements for front-end physical synthesis even more critical and challenging. The so-called peripheral approach of forcing macros to the periphery of the layout is no longer viable when the ratio of the sum of the macro perimeters to the floorplan perimeter is large, since this increases the required stacking depth of macros. In this paper, we develop a novel multilevel physical planning approach that exploits the hierarchy and dataflow inherent in the design RTL, and describe its realization in a new hierarchical macro placer, Hier-RTLMP. Hier-RTLMP borrows from traditional approaches used in manual system-on-chip (SoC) floorplanning to create an automatic macro placement for use with large IP blocks containing very large numbers of hard macros. Empirical studies demonstrate substantial improvements over the previous RTL-MP macro placement approach, and promising post-route improvements relative to a leading commercial place-and-route tool.

Motivation & Objective

• Address the growing challenge of macro placement in complex, auto-generated RTL designs—especially for ML accelerators—where traditional peripheral placement leads to excessive stacking depth and poor wirelength.
• Overcome the limitations of existing tools like RTL-MP, which fail on large designs with hundreds of macros and rely on single-level physical hierarchies.
• Enable automatic, high-quality macro placement that respects dataflow topology and supports efficient power grid generation by allowing macro tiling in the core area, not just the periphery.
• Develop a scalable, multilevel physical planning framework that mimics expert SoC floorplanning practices while being fully automatic and compatible with industrial P&R flows.

Proposed method

• Transform the logical RTL hierarchy into a multilevel physical hierarchy using an autoclustering engine that groups macros based on functional and dataflow relationships, with size-based thresholds for cluster creation at each level.
• Introduce a novel two-stage shaping engine: bottom-up analysis to determine feasible cluster shapes based on child clusters, followed by top-down refinement constrained by parent cluster outlines.
• Perform hierarchical macro placement level-by-level, placing and tiling macro groups within physical cluster boundaries to minimize wirelength and support routability.
• Use a weighted cost function combining normalized wirelength, timing slack (WNS/TNS), and congestion, with autotuning of parameters (e.g., segment count φ, boundary weight ζ) over 10–50 trials to optimize QoR.
• Integrate with Cadence Innovus 21.1 for full P&R flow validation, including clock tree synthesis and post-route optimization, to measure real-world PPA impact.
• Leverage the OpenROAD infrastructure for open-source deployment, with public runscripts and configuration support for reproducibility and community use.

(a)

Experimental results

Research questions

• RQ1 Can a hierarchical macro placer outperform peripheral-only placement in designs with hundreds of macros by enabling core-area tiling while preserving dataflow topology?
• RQ2 How does a multilevel physical hierarchy, derived from RTL logical hierarchy, improve scalability and placement quality compared to single-level approaches like RTL-MP?
• RQ3 To what extent can automated autotuning of placement parameters (φ, ζ) improve post-route timing and congestion metrics across diverse industrial and open-source designs?
• RQ4 Can a fully automatic macro placer achieve better PPA results than a commercial tool while reducing runtime by orders of magnitude?

Key findings

• Hier-RTLMP reduces runtime by 13× compared to RTL-MP on testcases where RTL-MP is still functional, demonstrating significant scalability improvements.
• For the Ariane (NG45) design, Hier-RTLMP achieves a 24% improvement in WNS (from -97 ps to -76 ps) and a 45% improvement in TNS (from -55 ns to -30 ns) post-route compared to the commercial tool.
• On the CA53 (GF12) design, Hier-RTLMP achieves a 10% reduction in normalized wirelength (from 1.08 to 1.07) and a 17% improvement in TNS (from -167 ns to -140 ns) compared to the commercial tool.
• Autotuning with 50 trials ($autotune_{50}^{*}$) consistently yields better post-route timing and wirelength than default or 10-trial tuning, with the best configurations found in the design space exploration.
• The best autotuned configurations ($autotune_{50}^{*}$) achieve WNS improvements of -76 ps (Ariane) and -0.25 ps (CA53), with minimal impact on area and power, confirming robustness across process nodes.
• Post-route layouts generated by Hier-RTLMP show improved congestion metrics, with average horizontal and vertical congestion reduced in key designs, indicating better routability.

(b)