[Paper Review] Importance of Diagonal Gates in Tensor Network Simulations

Danylo Lykov, Yuri Alexeev|arXiv (Cornell University)|Jun 29, 2021

Quantum Computing Algorithms and Architecture16 references4 citations

TL;DR

This paper introduces two optimization techniques—diagonal gate representation and ZZ-gate simplification—that dramatically accelerate tensor network simulations of Quantum Approximate Optimization Algorithm (QAOA) circuits. By restructuring the tensor network to exploit diagonal gates and decomposing ZZ gates, the authors achieve up to 10 million times speedup and extend feasible simulation depth from p=2 to p=5 and qubit count from 180 to 244 on supercomputers, significantly enhancing scalability for quantum advantage benchmarking.

ABSTRACT

In this work we present two techniques that tremendously increase the performance of tensor-network based quantum circuit simulations. The techniques are implemented in the QTensor package and benchmarked using Quantum Approximate Optimization Algorithm (QAOA) circuits. The techniques allowed us to increase the depth and size of QAOA circuits that can be simulated. In particular, we increased the QAOA depth from 2 to 5 and the size of a QAOA circuit from 180 to 244 qubits. Moreover, we increased the speed of simulations by up to 10 million times. Our work provides important insights into how various techniques can dramatically speed up the simulations of circuits.

Motivation & Objective

• To address the computational and memory bottlenecks in tensor network simulations of quantum circuits, particularly for variational quantum algorithms like QAOA.
• To improve the efficiency of classical simulation of large-scale quantum circuits by optimizing tensor network structure.
• To enable simulation of deeper and larger QAOA circuits than previously feasible using existing classical hardware.
• To provide practical, implementable techniques that reduce contraction width and computational cost in tensor network-based simulators.

Proposed method

• The authors implement a tensor network contraction approach in the QTensor simulator, focusing on QAOA circuits for MaxCut problems.
• They apply the Feynman path formalism to model quantum evolution and derive tensor network representations of circuit evolution.
• They introduce a diagonal gate optimization technique that rewrites single-qubit and two-qubit gates in a diagonal basis, reducing tensor rank and contraction complexity.
• They simplify ZZ-type entangling gates by expressing them as a sequence of diagonal operations, reducing the number of non-sparse tensors in the network.
• The optimization pipeline transforms the quantum circuit into a more compact tensor network with lower contraction width, enabling faster contraction order finding.
• The techniques are benchmarked using QAOA circuits on random 3-regular graphs, with performance measured in FLOPs and memory usage.

Figure 2: Line graphs of tensor networks for calculating QAOA ansatz state using different optimizations. “Default” and “diagonal” show line graphs of tensor network for the circuit shown in Figure 1 , using a full-matrix gates and diagonal gates approach, respectively. “ZZ gates + diagonal” is obta

Experimental results

Research questions

• RQ1 How can tensor network contraction efficiency be improved for simulating large-scale QAOA circuits?
• RQ2 To what extent do diagonal gate representations reduce tensor network complexity and simulation cost?
• RQ3 Can ZZ-gate simplification combined with diagonal gate optimization lead to significant speedups in quantum circuit simulation?
• RQ4 What is the maximum circuit depth and qubit count that can be simulated using optimized tensor network techniques on classical hardware?
• RQ5 How do these optimizations scale with increasing circuit size and depth?

Key findings

• The diagonal gate optimization alone reduces tensor network contraction width and enables simulation of larger circuits, with the most significant performance gains observed in deeper circuits.
• Combining diagonal gate representation with ZZ-gate simplification yields the highest speedup, achieving up to 10 million times faster simulation for p=5 QAOA circuits.
• The maximum QAOA depth p was increased from 2 to 5 on a supercomputer, extending the feasible simulation range for benchmarking quantum advantage.
• The maximum number of qubits for simulation increased from 180 to 244 on a supercomputer, with results verified on a laptop for smaller instances.
• The optimization techniques reduced memory requirements and enabled efficient simulation of single-amplitude evaluation for large QAOA circuits.
• The performance improvement scales with circuit size, indicating that diagonal gate optimization provides proportionally greater benefits for larger, more complex circuits.

Figure 3: Number of FLOPs to calculate a single amplitude of QAOA ansatz state for MaxCut using a different number of QAOA iterations. Each line shows a combination of optimization techniques, with “diagonal + ZZ gates” being the most advanced one. The shaded region shows 1- $\sigma$ interval over 5