[Paper Review] Memory Aware High-Level Synthesis for Embedded Systems

Gwenolé Corre, Eric Senn+2 more|arXiv (Cornell University)|May 30, 2006

Embedded Systems Design Techniques13 references3 citations

TL;DR

This paper proposes a memory-aware high-level synthesis (HLS) approach that integrates memory architecture constraints directly into the scheduling phase using a memory mapping file. By modeling memory constraints as formal constraints in the GAUT HLS tool, the method enables efficient exploration of trade-offs between area, power, and latency in real-time embedded systems with low computational complexity.

ABSTRACT

We introduce a new approach to take into account the memory architecture and the memory mapping in the High- Level Synthesis of Real-Time embedded systems. We formalize the memory mapping as a set of constraints used in the scheduling step. We use a memory mapping file to include those memory constraints in our HLS tool GAUT. Our scheduling algorithm exhibits a relatively low complexity that permits to tackle complex designs in a reasonable time. Finally, we show how to explore, with the help of GAUT, a wide range of solutions, and to reach a good tradeoff between time, power-consumption, and area.

Motivation & Objective

• To address the challenge of integrating memory architecture constraints into high-level synthesis for real-time embedded systems.
• To reduce scheduling complexity while supporting complex design exploration.
• To enable efficient trade-off analysis between area, power consumption, and execution time.
• To formalize memory mapping as constraints within the HLS flow for better design space exploration.
• To improve the practicality of HLS tools by incorporating realistic memory architectures early in the design process.

Proposed method

• The authors formalize memory mapping as a set of constraints integrated into the scheduling phase of the GAUT HLS tool.
• A memory mapping file is used to specify memory architecture details, such as memory types, sizes, and access latencies.
• The scheduling algorithm is designed with low computational complexity to handle complex designs efficiently.
• The approach enables exploration of multiple design points by varying scheduling and allocation decisions under memory constraints.
• Memory constraints are propagated through the synthesis flow to guide allocation and scheduling decisions.
• The method supports heterogeneous memory architectures, including on-chip and off-chip memory types.

Experimental results

Research questions

• RQ1 How can memory architecture constraints be effectively integrated into the high-level synthesis scheduling phase?
• RQ2 What is the impact of formalizing memory mapping as constraints on scheduling complexity and design exploration efficiency?
• RQ3 Can a low-complexity scheduling algorithm support complex embedded designs while maintaining memory-aware optimization?
• RQ4 How does the integration of memory constraints affect the trade-off between area, power, and latency in embedded systems?
• RQ5 To what extent can the proposed method explore diverse design solutions under memory architecture constraints?

Key findings

• The proposed method enables efficient exploration of design space with a low-complexity scheduling algorithm suitable for complex embedded systems.
• The integration of memory constraints via a memory mapping file improves the accuracy and practicality of high-level synthesis.
• The approach achieves a good trade-off between area, power consumption, and execution time across multiple design points.
• The use of formal constraints in scheduling allows for systematic exploration of memory-aware design alternatives.
• The method supports heterogeneous memory architectures, enabling better optimization for real-time embedded systems.
• The tool, GAUT, demonstrates feasibility in handling complex designs within reasonable time frames.