[Paper Review] Mitigating coherent leakage of superconducting qubits in a large-scale quantum socket

Thomas McConkey, J. H. Béjanin+5 more|arXiv (Cornell University)|Oct 12, 2017

Quantum Computing Algorithms and Architecture32 references3 citations

TL;DR

This paper proposes two methods—half-wave fencing and antinode pinning—using three-dimensional wires in a large-scale quantum socket to mitigate coherent leakage errors in superconducting qubits by detuning unwanted cavity modes from qubit frequencies. Simulations show these methods reduce coherent leakage to ~10⁻⁵, significantly below incoherent error rates, enabling scalable quantum computing with 100+ qubits.

ABSTRACT

A practical quantum computer requires quantum bit (qubit) operations with low error rates in extensible architectures. We study a packaging method that makes it possible to address hundreds of superconducting qubits by means of three-dimensional wires: The large-scale quantum socket. A qubit chip is housed in a superconducting box, where both box and chip dimensions lead to unwanted modes that can interfere with qubit operations. We theoretically analyze these interference effects in the context of qubit coherent leakage. We propose two methods to mitigate the resulting errors by detuning the resonance frequency of the modes from the qubit frequency. We perform detailed electromagnetic field simulations indicating that the resonance frequency of the modes increases with the number of installed three-dimensional wires and can be engineered to be significantly higher than the highest qubit frequency. Finally, we show preliminary experimental results towards the implementation of a large-scale quantum socket.

Motivation & Objective

• To address coherent leakage errors in large-scale superconducting qubit architectures caused by unwanted cavity modes in packaging.
• To develop a scalable packaging solution—large-scale quantum socket—using 3D wires for control and shielding.
• To mitigate coherent errors via frequency detuning of cavity modes from qubit frequencies using the same wires used for qubit operation.
• To demonstrate through simulations and preliminary experiments that 3D wires can both control qubits and suppress leakage into parasitic modes.
• To enable fault-tolerant quantum computing by reducing coherent errors below incoherent error thresholds.

Proposed method

• The paper models coherent leakage as a depolarizing channel induced by coupling to unwanted cavity modes in the quantum socket's metallic enclosure.
• It proposes half-wave fencing: positioning 3D wires at half-wavelength intervals to suppress mode amplitudes at qubit locations by destructive interference.
• It introduces antinode pinning: placing wires at antinodes of unwanted modes to shift their resonance frequency away from qubit frequencies.
• Electromagnetic field simulations are used to model Xmon transmon qubits coupled to cavity modes, with wire placement and geometry tuned to alter mode frequencies.
• The method leverages the same 3D wires used for qubit control to simultaneously isolate qubits from leakage by engineering mode spectra.
• The approach is generalized to chip modes and dielectric substrate modes by replacing wires with superconducting vias, maintaining frequency detuning.

Experimental results

Research questions

• RQ1 Can three-dimensional wires in a quantum socket simultaneously enable qubit control and suppress coherent leakage into unwanted cavity modes?
• RQ2 How does the resonance frequency of parasitic cavity modes scale with the number of 3D wires in the package?
• RQ3 To what extent can half-wave fencing and antinode pinning reduce coherent leakage errors in a large-scale quantum socket?
• RQ4 What is the relationship between qubit damping, Purcell effect, and the effectiveness of frequency detuning methods?
• RQ5 Can the same wire-based approach mitigate both box modes and chip modes in scalable superconducting qubit architectures?

Key findings

• The resonance frequency of unwanted cavity modes increases with the number of installed 3D wires, enabling engineering of modes well above the highest qubit frequency.
• Half-wave fencing and antinode pinning effectively suppress coherent leakage by detuning cavity modes from qubit frequencies, reducing error rates to approximately 10⁻⁵.
• Simulations confirm that 250 three-dimensional wires can achieve coherent leakage error rates of ~10⁻⁵, which are significantly lower than typical incoherent error rates.
• The 3D wires serve a dual role: enabling qubit control and providing electromagnetic shielding against parasitic modes.
• The frequency-shifting methods are applicable to both box modes and chip modes, including dielectric substrate modes, by replacing wires with superconducting vias.
• Preliminary experimental results demonstrate that strategic wire placement can create effective electric shielding against unwanted modes in a large-scale quantum socket.