[Paper Review] Particle Flow and PUPPI in the Level-1 Trigger at CMS for the HL-LHC

B. Kreis|arXiv (Cornell University)|Aug 6, 2018

Particle Detector Development and Performance4 references3 citations

TL;DR

This paper proposes implementing particle flow reconstruction and PUPPI pileup mitigation in the CMS Level-1 trigger for the HL-LHC using FPGAs, enabling particle-level reconstruction with tracking inputs to improve physics performance. Proof-of-principle FPGA implementations achieve 500 ns latency for particle flow and 100 ns for PUPPI, with 40% resource usage for four detector regions, demonstrating feasibility and significant improvements in MET and H_T trigger efficiency under high pileup (140 interactions).

ABSTRACT

With the planned addition of tracking information to the Compact Muon Solenoid (CMS) Level-1 trigger for the High-Luminosity Large Hadron Collider (HL-LHC), the trigger algorithms can be completely reconceptualized. We explore the feasibility of using particle flow-like reconstruction and pileup per particle identification (PUPPI) pileup mitigation at the hardware trigger level. This represents a new type of multi-subdetector pattern recognition challenge for the HL-LHC. We present proof-of-principle studies on both physics and hardware-resource performance of a prototype algorithm for use by CMS in the HL-LHC era.

Motivation & Objective

• Address the challenge of high pileup (up to 200 interactions) at the HL-LHC by improving trigger performance in the presence of background from additional proton interactions.
• Explore the integration of particle flow reconstruction and PUPPI pileup mitigation—state-of-the-art offline techniques—into the hardware-level Level-1 trigger for the first time.
• Assess the feasibility of implementing these complex algorithms in FPGAs under strict latency (2.5 μs) and resource constraints of the HL-LHC trigger system.
• Demonstrate that particle-level reconstruction with tracking inputs can significantly enhance trigger efficiency for key physics signatures like MET and H_T.

Proposed method

• Use tracking information from a new outer tracking subdetector and high-granularity calorimeter trigger primitives as inputs to the Level-1 trigger correlator.
• Implement a particle-flow reconstruction algorithm in FPGAs that links tracks and clusters based on ΔR and p_T matching to form particle-flow candidates (muons, electrons, photons, charged and neutral hadrons).
• Apply PUPPI pileup mitigation by identifying the primary vertex from p_T-weighted track z-distributions and computing neutral particle weights based on nearby non-pileup charged particles.
• Use a lookup table to map the sum of p_T/ΔR from non-pileup tracks to PUPPI weights for neutral particles.
• Process the detector in 0.55×0.55 η×φ regions with up to 25 tracks and 20 clusters per region, running multiple instances in parallel.
• Implement the algorithms using Xilinx Vivado High-Level Synthesis (2016.4) on a VU9P FPGA to evaluate resource usage and latency.

Experimental results

Research questions

• RQ1 Can particle flow reconstruction be effectively implemented in FPGAs for the CMS Level-1 trigger under 2.5 μs latency and 10 Tbps data bandwidth?
• RQ2 To what extent does integrating particle-level reconstruction and PUPPI pileup mitigation improve MET and H_T trigger performance under high pileup conditions?
• RQ3 What are the FPGA resource and latency requirements for a proof-of-principle implementation of particle flow and PUPPI in the Level-1 trigger?
• RQ4 How does the performance of a particle-flow-based trigger compare to traditional calorimeter-only or primary-vertex-track-based triggers in terms of efficiency and rate?
• RQ5 Is it feasible to adapt offline reconstruction algorithms like PUPPI and particle flow to the hardware trigger domain using current FPGA technology?

Key findings

• The particle flow algorithm achieves a latency of approximately 500 ns in FPGA implementation, meeting the 2.5 μs trigger latency budget.
• The PUPPI pileup mitigation algorithm achieves a latency of about 100 ns, enabling fast and efficient pileup suppression.
• Four detector regions (0.55×0.55 η×φ) can be processed using approximately 40% of the FPGA resources on a VU9P device.
• The particle-flow and PUPPI-based trigger achieves higher signal efficiency at fixed MET trigger rate (e.g., 20 kHz) compared to calorimeter-only or primary-vertex-track-based triggers.
• For H_T triggers, the particle-flow and PUPPI-based method shows superior turn-on performance at high H_T values, indicating better sensitivity to jet-rich final states.
• Simulations with 140 average pileup interactions show that the proposed method significantly improves MET trigger performance, reducing background contamination and improving signal selection.