[Paper Review] Quantized Feedback Control Software Synthesis from System Level Formal Specifications for Buck DC/DC Converters

Federico Mari, Igor Melatti+2 more|arXiv (Cornell University)|May 27, 2011

Embedded Systems Design Techniques5 references3 citations

TL;DR

This paper presents a formal model-based approach for automatically synthesizing correct-by-construction embedded control software for buck DC-DC converters using quantized feedback control. It leverages a tool called QKS to generate control software from system-level formal specifications (safety and liveness), plant models as discrete-time linear hybrid systems (DTLHS), and implementation constraints (e.g., number of AD bits), achieving worst-case execution time linear in the number of bits and ensuring robustness against parameter variations.

ABSTRACT

Many Embedded Systems are indeed Software Based Control Systems (SBCSs), that is control systems whose controller consists of control software running on a microcontroller device. This motivates investigation on Formal Model Based Design approaches for automatic synthesis of SBCS control software. In previous works we presented an algorithm, along with a tool QKS implementing it, that from a formal model (as a Discrete Time Linear Hybrid System, DTLHS) of the controlled system (plant), implementation specifications (that is, number of bits in the Analog-to-Digital, AD, conversion) and System Level Formal Specifications (that is, safety and liveness requirements for the closed loop system) returns correct-by-construction control software that has a Worst Case Execution Time (WCET) linear in the number of AD bits and meets the given specifications. In this technical report we present full experimental results on using it to synthesize control software for two versions of buck DC-DC converters (single-input and multi-input), a widely used mixed-mode analog circuit.

Motivation & Objective

• To address the challenge of manually designing correct and efficient control software for embedded systems, particularly in safety-critical applications like power electronics.
• To enable automatic synthesis of control software that is formally guaranteed to meet system-level safety and liveness specifications.
• To ensure the generated software has predictable and bounded worst-case execution time (WCET) linear in the number of analog-to-digital (AD) conversion bits.
• To support robust controller synthesis by accounting for expected variations in key parameters such as input voltage and load.

Proposed method

• Model the plant (buck converter) as a Discrete Time Linear Hybrid System (DTLHS) to capture both continuous dynamics and discrete control logic.
• Formalize system-level specifications as safety and liveness properties over the closed-loop system behavior.
• Use quantization constraints (number of AD bits) as implementation parameters to bound the state space and enable efficient synthesis.
• Employ Mixed-Integer Linear Programming (MILP) solvers within the QKS tool to compute control laws and controllable regions that satisfy formal specifications.
• Synthesize C code with bounded worst-case execution time (WCET) linear in the number of AD bits, ensuring real-time feasibility.
• Generate guaranteed operational regions (controlled regions) to ensure fault detection and recovery in case of state violations.

Experimental results

Research questions

• RQ1 Can formal model-based synthesis generate correct-by-construction control software for buck DC-DC converters with predictable worst-case execution time?
• RQ2 How does the number of AD bits affect the synthesis performance and control software complexity?
• RQ3 Can the approach generate robust controllers that tolerate variations in input voltage and load parameters?
• RQ4 What is the scalability of the synthesis process with respect to the number of inputs in multi-input buck converters?
• RQ5 How efficiently can the QKS tool solve the underlying MILP problems for real-world power converter models?

Key findings

• For the single-input buck converter, the QKS tool successfully generated correct-by-construction control software with WCET linear in the number of AD bits, achieving a total synthesis time of 2.88e+04 seconds and 6.41e+07 bytes of memory for b=8 bits.
• The multi-input buck converter synthesis scaled with the number of inputs: for n=4 inputs, the total CPU time reached 6.43e+05 seconds and memory usage was 9.51e+07 bytes, with a successful synthesis outcome (μ = Sol).
• The number of MILP instances solved grew significantly with the number of inputs, e.g., 5.5e+07 instances for n=4 in MILP type 5, with a total time of 1.1e+05 seconds.
• Controlled regions (guaranteed operational ranges) were successfully computed and visualized for both single-input and multi-input buck converters across varying bit-widths (b=8 to b=11) and input counts (n=1 to n=4).
• The synthesis process remained scalable and correct across all tested configurations, with no failures (all μ = Sol) and no timeouts reported.
• The average time per MILP instance remained under 10ms for most types, indicating efficient solving performance even at scale.