[Paper Review] Single Spin Logic Implementation of VLSI Adders

Soumitra Shukla, Bahniman Ghosh|arXiv (Cornell University)|Nov 22, 2011

Quantum and electron transport phenomena11 references3 citations

TL;DR

This paper proposes the implementation of VLSI adder circuits using Single Spin Logic (SSL) based on quantum dots (qds) and Spin-Polarized Scanning Tunneling Microscopy (SPSTM). It demonstrates that while the mirror adder in SSL offers no advantage over CMOS, the transmission gate, static, and dynamic Manchester carry adders in SSL significantly reduce complexity and qd count—aligning with trends seen in conventional transistor-based adders.

ABSTRACT

Some important VLSI adder circuits are implemented using quantum dots (qd) and Spin Polarized Scanning Tunneling Microscopy (SPSTM) in Single Spin Logic (SSL) paradigm. A simple comparison between these adder circuits shows that the mirror adder implementation in SSL does not carry any advantage over CMOS adder in terms of complexity and number of qds, opposite to the trend observed in their charge-based counterparts. On the contrary, the transmission gate adder, Static and Dynamic Manchester carry gate adders in SSL reduce the complexity and number of qds, in harmony with the trend shown in transistor adders.

Motivation & Objective

• To explore the feasibility of implementing VLSI adder circuits using the Single Spin Logic (SSL) paradigm.
• To compare SSL-based adder designs with their CMOS counterparts in terms of circuit complexity and quantum dot (qd) count.
• To evaluate whether SSL offers advantages in area and complexity for adder architectures, particularly in comparison to charge-based counterparts.
• To identify which adder topologies in SSL achieve improved efficiency relative to CMOS implementations.
• To analyze the scalability and practicality of SSL-based adders for future low-power VLSI systems.

Proposed method

• Design and simulate key VLSI adder circuits—mirror adder, transmission gate adder, and static/dynamic Manchester carry gate adders—within the Single Spin Logic (SSL) framework.
• Utilize quantum dots (qds) as spin-based logic elements, with spin states representing binary information (0 or 1).
• Employ Spin-Polarized Scanning Tunneling Microscopy (SPSTM) for initializing, reading, and manipulating individual electron spins in qds.
• Model the logic operations using spin-dependent tunneling and controlled exchange interactions between qds.
• Quantify circuit complexity by counting the number of qds and interconnections required for each adder type.
• Compare the resulting qd counts and structural complexity across SSL adders and equivalent CMOS designs.

Experimental results

Research questions

• RQ1 Does the mirror adder in the Single Spin Logic (SSL) paradigm offer any advantage over CMOS in terms of complexity or qd count?
• RQ2 Can SSL-based transmission gate and Manchester carry adders reduce circuit complexity compared to their CMOS equivalents?
• RQ3 Do the trends in complexity reduction observed in transistor-based adders also hold in spin-based SSL adders?
• RQ4 What is the impact of spin-polarized tunneling and quantum dot integration on the scalability of SSL adders?
• RQ5 Which SSL adder architecture achieves the best trade-off between logic functionality, qd count, and structural simplicity?

Key findings

• The mirror adder in SSL does not reduce complexity or qd count compared to CMOS, contradicting trends seen in charge-based counterparts.
• The transmission gate adder in SSL achieves lower circuit complexity and fewer quantum dots than its CMOS equivalent.
• Both static and dynamic Manchester carry gate adders in SSL demonstrate reduced complexity and qd count, consistent with trends in transistor-based adders.
• SSL implementations of these adders show potential for scalable, low-power VLSI logic due to reduced qd requirements.
• The results confirm that spin-based logic can achieve efficiency gains in specific adder architectures, particularly those with optimized carry propagation.
• The study establishes that not all adder types in SSL offer advantages—only those with efficient carry logic, such as Manchester carry, show significant improvements.