[Paper Review] Static extraction of memory access profiles for multi-core interference analysis of real-time tasks

Thomas Carle, Hugues Cassé|arXiv (Cornell University)|Mar 31, 2021

Real-Time Systems Scheduling14 references4 citations

TL;DR

This paper presents a static analysis framework that extracts worst-case timing and memory access profiles for real-time tasks running on multi-core processors by analyzing binary code in isolation. It enables precise interference-aware Worst-Case Response Time (WCRT) analysis by generating abstracted segment sequences and timed traces, which can be fed into existing WCRT and real-time calculus back-ends, offering a sound, precise, and reusable input pipeline for multi-core real-time systems.

ABSTRACT

We present a static analysis framework for real-time task systems running on multi-core processors. Our method analyzes tasks in isolation at the binary level and generates worst-case timing and memory access profiles. These profiles can then be combined to perform an interference analysis at the task system level, as part of a multi-core Worst-Case Response Time (WCRT) analysis. In this paper we introduce a formal description of the models and algorithmic building blocks composing our framework. We also discuss how the memory access profiles generated by our method could be used to feed existing state-of-the-art WCRT frameworks. To the best of our knowledge, it is the first time that a method is documented on how to produce sound, safe and precise inputs for interference analysis methods.

Motivation & Objective

• To address the challenge of multi-core timing interference in real-time systems, where shared memory buses cause unpredictable delays during parallel execution.
• To provide a method that generates sound, safe, and precise worst-case memory access and timing profiles for tasks without requiring source code modifications.
• To enable integration with existing WCRT analysis frameworks by producing standardized, abstracted inputs such as segment sequences and timed traces.
• To support legacy and COTS-based systems by operating at the binary level with minimal code transformation.
• To offer a general-purpose input generation pipeline for state-of-the-art WCRT and real-time calculus back-ends, improving precision and reusability.

Proposed method

• The framework performs static binary-level analysis of real-time tasks to extract worst-case execution traces, modeling memory access patterns with time-stamped instructions.
• It applies a formal abstraction process to convert low-level traces into higher-level segment sequences, each characterized by a duration and a worst-case number of memory accesses.
• The algorithm uses a time-ordered segmentation process that accounts for access duration and inter-access timing, preserving worst-case behavior across overlapping access patterns.
• It supports both fine-grained trace enumeration and coarse-grained segment abstraction, allowing trade-offs between precision and computational cost.
• The framework ensures over-approximation safety by conservatively modeling memory access windows and bus arbitration delays.
• It enables integration with existing WCRT back-ends by providing inputs compatible with interference models in real-time calculus and multi-core response time analysis.

Experimental results

Research questions

• RQ1 How can worst-case memory access profiles be statically extracted from binary code for multi-core real-time tasks with minimal assumptions?
• RQ2 What formal models and abstractions can preserve timing and access precision while enabling reuse across different WCRT analysis back-ends?
• RQ3 How can the generated profiles be used to accurately model interference from shared memory buses in multi-core systems?
• RQ4 What is the trade-off between precision (trace-level) and efficiency (segment-level) in representing memory access profiles?
• RQ5 How can the framework be adapted to work with existing WCRT and real-time calculus tools without requiring changes to their core algorithms?

Key findings

• The framework successfully generates sound and precise worst-case memory access and timing profiles from binary code, enabling accurate interference modeling in multi-core systems.
• The abstraction of traces into segment sequences reduces complexity while preserving worst-case guarantees, making it suitable for integration with existing WCRT back-ends.
• The method supports both fine-grained trace enumeration and coarse-grained segment abstraction, offering a tunable trade-off between precision and computational cost.
• The generated profiles are compatible with state-of-the-art WCRT analysis frameworks, including those based on real-time calculus and interference formulas.
• The approach enables static scheduling and response time analysis on COTS processors without requiring source code changes or hardware modifications.
• The framework provides a reusable, standardized input pipeline for interference-aware analysis, filling a critical gap in current multi-core real-time analysis toolchains.