[Paper Review] Synthesis of AMBA AHB from Formal Specification

Yashdeep Godhal, Krishnendu Chatterjee+1 more|arXiv (Cornell University)|Jan 16, 2010

Formal Methods in Verification8 references3 citations

TL;DR

This paper presents a formal synthesis approach for the complete AMBA AHB protocol—including the Arbiter, Master, and Slave components—using Property Specification Language (PSL) and GR(1) synthesis. It achieves order-of-magnitude improvements in synthesis time and gate count by refining formal specifications, demonstrating that systematic specification writing enables automatic, compact, and correct-by-construction hardware generation for industrial protocols.

ABSTRACT

The standard procedure for hardware design consists of describing circuit in a hardware description language at logic level followed by extensive verification and logic-synthesis. However, this process consumes significant time and needs a lot of effort. An alternative is to use formal specification language as a high-level hardware description language and synthesize hardware from formal specification. Bloem et.al. gave formal specifications and synthesize the AMBA AHB Arbiter. Our contributions are as follows:(1) We present more complete and compact formal specifications for the AMBA AHB Arbiter, and obtain significant (order of magnitude) improvement in synthesis results (both with respect to time and the number of gates of the synthesize circuit); (2) we present formal specification and synthesize to generate compact circuits for the remaining two components of the AMBA AHB protocol, namely, the AMBA AHB Master and AMBA AHB Slave; and (3) from the lessons learnt we present few principles for writing formal specifications for efficient hardware synthesis. Thus with intelligently written complete formal specifications we are able to automatically synthesize an important and widely used industrial protocol.

Motivation & Objective

• To develop a systematic method for synthesizing complete, industrial-grade hardware protocols from formal specifications.
• To improve synthesis efficiency and circuit compactness for the AMBA AHB protocol by refining formal specifications.
• To extend prior work limited to the AHB Arbiter by synthesizing the AHB Master and Slave components for the first time.
• To derive general principles for writing efficient formal specifications that enable scalable and performant hardware synthesis.

Proposed method

• Formal specifications for the AHB Arbiter, Master, and Slave are expressed in Property Specification Language (PSL), focusing on safety and liveness properties.
• The synthesis process leverages GR(1) realizability and synthesis techniques, which enable polynomial-time synthesis for a broad class of reactive systems.
• Specifications are iteratively refined: starting with simplified designs (e.g., 1-bit data width), then incrementally adding complexity to achieve full functionality.
• Auxiliary signals are introduced to model complex behaviors such as memory interactions in the AHB Slave, improving specification expressiveness and synthesis feasibility.
• The final specifications are automatically synthesized into gate-level circuits using the Anzu tool, with subsequent area optimization via ABC.
• Synthesis results are evaluated based on runtime, gate count, and circuit area, with comparisons to prior work.

Experimental results

Research questions

• RQ1 Can a complete, industrial-grade AMBA AHB protocol be automatically synthesized from formal specifications?
• RQ2 How can formal specifications be structured to achieve efficient and compact hardware synthesis?
• RQ3 What are the key challenges in synthesizing control-intensive components like the AHB Master and Slave, and how can they be addressed?
• RQ4 To what extent do specification simplification and incremental refinement improve synthesis performance?

Key findings

• The synthesis of the AHB Slave took 21.5 seconds and produced a circuit with 214 gates and an area of 429 unit squared, demonstrating high compactness.
• The refined formal specifications for the AHB Arbiter led to order-of-magnitude improvements in both synthesis time and gate count compared to prior work.
• The AHB Master and Slave were synthesized for the first time from formal specifications, extending the scope of prior synthesis work limited to the Arbiter.
• The use of auxiliary signals significantly improved the expressiveness and feasibility of specifying complex behaviors such as memory access and data latching.
• Iterative specification refinement—starting from simplified models and incrementally adding complexity—proved essential for achieving efficient synthesis.
• The lessons learned, including structured specification writing and event-order modeling, provide practical principles for efficient formal hardware synthesis.