[Paper Review] TAPA: A Scalable Task-Parallel Dataflow Programming Framework for Modern FPGAs with Co-Optimization of HLS and Physical Design

Licheng Guo, Yuze Chi+10 more|arXiv (Cornell University)|Sep 6, 2022

Embedded Systems Design Techniques71 references4 citations

TL;DR

TAPA is a task-parallel dataflow programming framework for modern FPGAs that co-optimizes high-level synthesis (HLS) and physical design through coarse-grained floorplanning, enabling significant frequency improvements. It boosts average frequency from 147 MHz to 297 MHz (102% improvement) across 43 designs with negligible area overhead and restores timing closure for 16 previously unroutable designs.

ABSTRACT

In this paper, we propose TAPA, an end-to-end framework that compiles a C++ task-parallel dataflow program into a high-frequency FPGA accelerator. Compared to existing solutions, TAPA has two major advantages. First, TAPA provides a set of convenient APIs that allow users to easily express flexible and complex inter-task communication structures. Second, TAPA adopts a coarse-grained floorplanning step during HLS compilation for accurate pipelining of potential critical paths. In addition, TAPA implements several optimization techniques specifically tailored for modern HBM-based FPGAs. In our experiments with a total of 43 designs, we improve the average frequency from 147 MHz to 297 MHz (a 102% improvement) with no loss of throughput and a negligible change in resource utilization. Notably, in 16 experiments we make the originally unroutable designs achieve 274 MHz on average. The framework is available at https://github.com/UCLA-VAST/tapa and the core floorplan module is available at https://github.com/UCLA-VAST/AutoBridge.

Motivation & Objective

• Address the growing challenge of timing closure in high-level synthesis (HLS) for modern, heterogeneous FPGAs with multi-die architectures and HBM.
• Overcome the disconnect between HLS and physical design by integrating floorplanning into the HLS compilation flow.
• Enable scalable, high-frequency task-parallel dataflow programs on HBM-equipped FPGAs through co-optimization of HLS and physical design.
• Provide a practical, user-friendly API for expressing complex inter-task communication patterns in C++.
• Restore timing closure for designs that previously failed to route due to critical path delays.

Proposed method

• Introduce a coarse-grained floorplanning step during HLS compilation to guide accurate pipelining of critical paths across inter-die and long interconnects.
• Co-optimize HLS and physical design by using floorplanning information to insert registers on long, timing-critical paths, especially across die boundaries.
• Implement automatic HBM port binding and customized programming APIs to minimize area overhead of HBM I/O modules.
• Explore the floorplan solution space to co-optimize task placement and interconnect routing for improved timing.
• Use a conservative latency-balancing strategy across reconvergent paths to maintain throughput while improving frequency.
• Integrate with commercial FPGA toolchains to ensure compatibility and practical deployment.

Experimental results

Research questions

• RQ1 How can HLS and physical design be co-optimized to improve timing closure in modern, multi-die FPGAs?
• RQ2 What impact does coarse-grained floorplanning during HLS compilation have on frequency and routability?
• RQ3 Can co-optimization techniques effectively address the timing challenges introduced by HBM and heterogeneous resources in FPGAs?
• RQ4 To what extent can TAPA restore timing closure for designs that were previously unroutable?
• RQ5 How does the integration of floorplanning with HLS affect the performance and resource utilization of task-parallel dataflow programs?

Key findings

• TAPA improves the average frequency of 43 designs from 147 MHz to 297 MHz, representing a 102% improvement with no loss in throughput.
• In 16 experiments, TAPA successfully achieved timing closure for designs that were previously unroutable, achieving an average frequency of 274 MHz.
• The framework maintains negligible changes in resource utilization while significantly improving timing performance.
• The co-optimization of HLS and physical design enables effective pipelining of long cross-die interconnects, which are major timing bottlenecks in modern FPGAs.
• TAPA’s floorplanning and HBM-aware optimizations reduce area overhead of HBM I/O modules and improve routing efficiency.
• The framework has been successfully applied in multiple real-world projects, demonstrating its practicality and effectiveness in high-performance FPGA acceleration.