[Paper Review] The BaseJump Manycore Accelerator Network

Shaolin Xie, Michael Taylor|arXiv (Cornell University)|Aug 2, 2018

Interconnection Networks and Systems2 references4 citations

TL;DR

The BaseJump Manycore Accelerator Network is an open-source, mesh-based on-chip network designed for RISC-V compatible manycore systems, enabling efficient remote memory operations via a partitioned global address space model. It supports remote load, store, and atomic swap operations with minimal hardware, achieving high performance for scatter/gather workloads and scalable communication through dimension-ordered routing and credit-based flow control.

ABSTRACT

The BaseJump Manycore Accelerator-Network is an open source mesh-based On-Chip-Network which is designed leveraging the Bespoke Silicon Group's 20+ years of experience in designing manycore architectures. It has been used in the 16nm 511-core RISC-V compatible Celerity chip Davidson et al. (2018), forming the basis of both a 1 GHz 496-core RISC-V manycore and a 10-core always-on low voltage complex. It was also used in the 180nm BSG Ten chip, which featured ten cores and a mesh that extends over off-chip links to an FPGA. To facilitate use by the open source community of the BaseJump Manycore network, we explain the ideas, protocols, interfaces and potential uses of the mesh network. We also show an example with source code that demonstrates how to integrate user designs into the mesh network.

Motivation & Objective

• To provide a scalable, open-source on-chip network for manycore accelerators with minimal area and energy overhead.
• To support efficient remote memory access patterns such as random scatter and gather operations in a partitioned global address space model.
• To enable seamless integration of diverse accelerators—ranging from RISC-V cores to DSPs and eFPGAs—into a unified mesh-based communication fabric.
• To offer both simple and advanced integration modes: a standard endpoint for basic load/store operations and low-level network-aware design for streaming RPC-style workloads.
• To analyze and quantify network performance under uniform random, transpose, and nearest-neighbor traffic patterns using dimension-ordered routing and bisection bandwidth limits.

Proposed method

• Employs a 2D mesh topology with dimension-ordered routing and minimal buffers to reduce area and energy consumption.
• Uses a single-wide 32-bit packet format with header fields for operation type (load, store, swap), source/destination coordinates, and data payload.
• Implements credit-based flow control to manage network congestion and ensure reliable delivery of request and reply packets.
• Supports remote memory operations via a partitioned global address space model using (X, Y, local_address) addressing, enabling load, store, and compare-and-swap across tiles.
• Provides a standard endpoint module that abstracts network complexity for accelerators performing simple remote memory accesses.
• Enables advanced streaming workloads through direct network interface design, allowing accelerators to process incoming requests as streaming RPCs with pipelined operation.

Experimental results

Research questions

• RQ1 How can a low-area, low-energy on-chip network be designed to support high-performance remote memory operations in a manycore system?
• RQ2 What are the performance limits of a minimal mesh network under uniform random traffic, and how do they scale with network size?
• RQ3 How does dimension-ordered routing compare to adaptive algorithms (e.g., Valiant, ROMM) in terms of average packet delay under different communication patterns?
• RQ4 What mechanisms enable efficient integration of accelerators with varying computational models—especially those requiring streaming or atomic operations—into a shared network fabric?
• RQ5 To what extent can network performance be predicted using bisection bandwidth and offered traffic metrics in a mesh topology?

Key findings

• For a 16×16 mesh, the network can sustain a new message injection every 4 cycles under uniform random traffic, limited by a bisection bandwidth of 16 links and a theoretical maximum of 4 messages per cycle per link.
• Under uniform random traffic, the average round-trip latency for a 16×16 mesh is approximately 48 cycles, with relative underutilization of only 3× when all cores are sending messages across the bisection.
• Dimension-ordered routing (DOR) performs poorly under transpose traffic patterns, while being highly efficient for nearest-neighbor communication, as shown in comparative simulations.
• The network achieves high throughput for random scatter operations due to minimal blocking hardware and one-word-per-cycle remote store throughput.
• Remote load and compare-and-swap operations incur long latencies due to round-trip communication, but can be mitigated through data locality or parallelization across multiple tiles.
• The network’s performance is bounded by bisection bandwidth: in a 16×16 mesh, only 32 remote operations can be sustained per cycle across the bisection, limiting execution efficiency for high-concurrency workloads.