[Paper Review] TinyDefectNet: Highly Compact Deep Neural Network Architecture for High-Throughput Manufacturing Visual Quality Inspection

Mohammad Javad Shafiee, Mahmoud Famouri+3 more|arXiv (Cornell University)|Nov 28, 2021

Industrial Vision Systems and Defect Detection4 citations

TL;DR

TinyDefectNet is a highly compact deep convolutional neural network architecture designed for high-throughput manufacturing visual quality inspection, using machine-driven generative synthesis to achieve state-of-the-art defect detection accuracy with only ~427K parameters and ~97M FLOPs. It delivers 9× faster inference than ResNet-50 via native TensorFlow and 9× speedup with AMD ZenDNN, while maintaining 98% accuracy and enabling trust through explainability-driven validation.

ABSTRACT

A critical aspect in the manufacturing process is the visual quality inspection of manufactured components for defects and flaws. Human-only visual inspection can be very time-consuming and laborious, and is a significant bottleneck especially for high-throughput manufacturing scenarios. Given significant advances in the field of deep learning, automated visual quality inspection can lead to highly efficient and reliable detection of defects and flaws during the manufacturing process. However, deep learning-driven visual inspection methods often necessitate significant computational resources, thus limiting throughput and act as a bottleneck to widespread adoption for enabling smart factories. In this study, we investigated the utilization of a machine-driven design exploration approach to create TinyDefectNet, a highly compact deep convolutional network architecture tailored for high-throughput manufacturing visual quality inspection. TinyDefectNet comprises of just ~427K parameters and has a computational complexity of ~97M FLOPs, yet achieving a detection accuracy of a state-of-the-art architecture for the task of surface defect detection on the NEU defect benchmark dataset. As such, TinyDefectNet can achieve the same level of detection performance at 52$\ imes$ lower architectural complexity and 11x lower computational complexity. Furthermore, TinyDefectNet was deployed on an AMD EPYC 7R32, and achieved 7.6x faster throughput using the native Tensorflow environment and 9x faster throughput using AMD ZenDNN accelerator library. Finally, explainability-driven performance validation strategy was conducted to ensure correct decision-making behaviour was exhibited by TinyDefectNet to improve trust in its usage by operators and inspectors.

Motivation & Objective

• To address the challenge of deploying efficient deep learning models in high-throughput manufacturing environments with strict computational and latency constraints.
• To overcome the limitations of off-the-shelf models like ResNet-50, which are too large and slow for real-time industrial deployment.
• To develop a highly compact, accurate, and efficient deep learning architecture tailored specifically for surface defect detection in manufacturing.
• To ensure model reliability and operator trust through explainability-driven performance validation.
• To demonstrate the effectiveness of machine-driven design exploration using generative synthesis for industrial computer vision applications.

Proposed method

• Employed generative synthesis—a machine-driven design exploration approach—using a generator-inquisitor pair to automatically search for optimal micro- and macro-architectural components.
• Formulated the architecture design as a constrained optimization problem, iteratively refining candidate architectures based on performance and efficiency metrics.
• Trained and evaluated the final architecture on the NEU Surface Defect Benchmark dataset for surface defect detection.
• Deployed TinyDefectNet on an AMD EPYC 7R32 CPU and leveraged the ZenDNN accelerator library to enhance inference speed without model recompilation.
• Applied a quantitative explainability strategy from prior work to audit decision-making and ensure predictions are based on relevant defect features.
• Optimized inference performance using tuned ZenDNN environment variables, including memory pooling and thread affinity settings.

Experimental results

Research questions

• RQ1 Can a machine-driven design exploration strategy generate a deep neural network architecture that achieves state-of-the-art accuracy while being significantly smaller and faster than off-the-shelf models for manufacturing defect inspection?
• RQ2 How does the proposed TinyDefectNet architecture compare in inference speed and model complexity to standard architectures like ResNet-50 in real-world deployment scenarios?
• RQ3 To what extent can the ZenDNN accelerator library improve the inference throughput of TinyDefectNet on AMD CPUs without requiring model conversion?
• RQ4 Does the explainability-driven validation strategy effectively confirm that TinyDefectNet’s decisions are based on actual defect-relevant visual features?
• RQ5 Can the generative synthesis approach reliably produce compact, high-performing models tailored for industrial visual inspection tasks?

Key findings

• TinyDefectNet achieves 98% detection accuracy on the NEU Surface Defect Benchmark, matching the performance of ResNet-50 despite being significantly more compact.
• The model has only ~427K parameters and ~97M FLOPs, representing a 52× reduction in architectural complexity and 11× reduction in computational complexity compared to ResNet-50.
• On an AMD EPYC 7R32 CPU, TinyDefectNet achieves 7.6× faster inference than ResNet-50 in native TensorFlow, reducing inference time from 19 ms to 2.5 ms per image.
• When deployed with the ZenDNN accelerator library, TinyDefectNet achieves 9× faster inference than ResNet-50 in native TensorFlow, reducing inference time to approximately 2 ms.
• The explainability-driven validation confirmed that TinyDefectNet correctly identifies scratch defects by focusing on relevant defect patterns, enhancing model trustworthiness.
• Optimal ZenDNN configuration (e.g., mempool enable, thread affinity) further improved performance, with 1.2× speedup over native inference, demonstrating the impact of runtime tuning.