[Paper Review] Constant-Overhead Fault-Tolerant Quantum Computation with Reconfigurable Atom Arrays

Qian Xu, J. Pablo Bonilla Ataides+8 more|arXiv (Cornell University)|Aug 16, 2023

Quantum Computing Algorithms and Architecture14 citations

TL;DR

The paper proposes a hardware-efficient scheme using reconfigurable neutral-atom arrays to implement high-rate qLDPC codes (HGP and LP) for fault-tolerant quantum computation with effectively constant overhead, showing favorable small-scale performance over surface codes.

ABSTRACT

Quantum low-density parity-check (qLDPC) codes can achieve high encoding rates and good code distance scaling, providing a promising route to low-overhead fault-tolerant quantum computing. However, the long-range connectivity required to implement such codes makes their physical realization challenging. Here, we propose a hardware-efficient scheme to perform fault-tolerant quantum computation with high-rate qLDPC codes on reconfigurable atom arrays, directly compatible with recently demonstrated experimental capabilities. Our approach utilizes the product structure inherent in many qLDPC codes to implement the non-local syndrome extraction circuit via atom rearrangement, resulting in effectively constant overhead in practically relevant regimes. We prove the fault tolerance of these protocols, perform circuit-level simulations of memory and logical operations with these codes, and find that our qLDPC-based architecture starts to outperform the surface code with as few as several hundred physical qubits at a realistic physical error rate of $10^{-3}$. We further find that less than 3000 physical qubits are sufficient to obtain over an order of magnitude qubit savings compared to the surface code, and quantum algorithms involving thousands of logical qubits can be performed using less than $10^5$ physical qubits. Our work paves the way for explorations of low-overhead quantum computing with qLDPC codes at a practical scale, based on current experimental technologies.

Motivation & Objective

• Motivate the use of high-rate qLDPC codes to reduce quantum resource overhead compared to surface codes.
• Develop a hardware-efficient neutral-atom implementation exploiting the product structure of qLDPC codes.
• Analyze circuit-level fault tolerance and memory performance with HGP and LP codes in realistic noise models.
• Demonstrate potential qubit savings and thresholds relative to surface codes for practical qubit counts.

Proposed method

• Leverage the product structure of qLDPC codes to implement non-local syndrome extraction via atom rearrangement in reconfigurable atom arrays.
• Use a space-time circuit-level decoder based on belief propagation and ordered statistics decoding (BP+OSD) for joint decoding across multiple code cycles.
• Employ a single-shot syndrome extraction circuit with a depolarizing noise model and include idling errors in simulations.
• Demonstrate syndrome extraction using parallel row/column permutations compatible with acousto-optic deflector (AOD) based hardware.
• Propose a memory-processor-ancilla architecture enabling teleportation of logical information between qLDPC memory and topological processor patches during computation.
• Provide threshold proofs and numerical simulations for HGP and LP codes under circuit-level noise, with comparisons to surface codes.

Experimental results

Research questions

• RQ1 Can high-rate qLDPC codes (HGP and LP) provide fault-tolerant quantum computation with constant overhead on reconfigurable atom arrays?
• RQ2 What are the circuit-level thresholds and logical failure rates for HGP and LP qLDPC memories under realistic noise (including idling) in atom-array hardware?
• RQ3 How does the qubit overhead of qLDPC memories compare to surface codes for a target number of logical qubits and logics failure rates?
• RQ4 Is fault-tolerant universal computation achievable with qLDPC codes via teleportation and lattice surgery between memory and processor patches while maintaining low overhead?

Key findings

• HGP and LP qLDPC codes achieve circuit-level thresholds around 0.6–0.63% under depolarizing noise without idling, and maintain good sub-threshold scaling.
• With idling errors at a physical error rate of 1e-3, these codes still outperform the surface code in qubit overhead for practical sizes (e.g., less than 3000 physical qubits for several tens of logical qubits).
• For as few as 25 logical qubits, both HGP and LP codes show improvement over surface codes in required physical qubits; LP codes show stronger sub-threshold scaling at finite sizes.
• LP codes can achieve over an order of magnitude qubit savings over surface codes with under 3000 physical qubits for <200 logical qubits.
• For larger scales, HGP codes extrapolate to >1e5 physical qubits for 1000 logical qubits, maintaining significant space savings.
• Logical operations via teleportation between memory and ancillary topological codes preserve the high thresholds and low overhead in the computation setting.