[Paper Review] DSAC: Low-Cost RowHammer Mitigation Using In-DRAM Stochastic and Approximate Counting Algorithm

Seungki Hong, Dongha Kim+5 more|arXiv (Cornell University)|Feb 7, 2023

Low-power high-performance VLSI design15 citations

TL;DR

DSAC introduces in-DRAM Stochastic and Approximate Counting with Time-Weighted Counting to mitigate Rowhammer and Passing Gate Effect, achieving 49x lower Maximum Disturbance than prior counter-based methods.

ABSTRACT

This paper provides the fundamental mechanisms of two types of row activation-induced bit flips and proposes in-DRAM protection techniques. RowBleed occurs when a victim row experiences charge leakage due to transistor's threshold voltage lowering induced by long activation of a neighboring aggressor row. Therefore, this paper proposes Time-Weighted Counting for RowBleed mitigation, which assigns greater counter weights to rows that are activated for longer durations. On the other hand, RowHammer occurs when a victim row experiences electron injection due to frequent activation of a neighboring aggressor row. Similarly, Extended RowHammer, the phenomenon where victim rows are two rows beyond aggressor rows, is also caused by electron injection due to frequent activation of a neighboring aggressor row. Consequently, accurate detection of aggressor rows is crucial. Therefore, this paper proposes RowHammer mitigation algorithm named DSAC (in-DRAM Stochastic and Approximate Counting algorithm), which utilizes a replacement probability that adjusts based on the count of the old row. This paper introduces a RowHammer protection index called Maximum Disturbance, which measures the maximum accumulated number of row activations within an observation period. The experimental results demonstrate that DSAC can achieve 133x lower Maximum Disturbance than the state-of-the-art counter-based algorithm.

Motivation & Objective

• Understand two activation-induced bit-flips (Passing Gate Effect and Rowhammer) and their system-level impact.
• Propose in-DRAM DSAC to filter out decoy-rows using stochastic replacement and approximate counting.
• Mitigate Passing Gate Effect with Time-Weighted Counting.
• Develop adaptive TRR threshold (TRR_TH) linked to MPA_tREFIe to handle MR4-enabled systems.

Proposed method

• Introduce in-DRAM DSAC with stochastic replacement to filter decoy-rows.
• Apply Approximate Counting (Space-Saving style) to reduce area.
• Implement Time-Weighted Counting with W_C = alpha * log2(tRAS / tRASmin) to mitigate Passing Gate Effect.
• Define adaptive TRR_TH based on RH_TH and MPA_tREFIe to cope with MR4.
• Present architecture with four count tables, PRNG seed mixer, LFSR, Probability LUT, and a DSAC algorithm with P(r) = 1 / (min_cnt + 1).
• Provide pseudocode and analysis showing Ce (count error) bounds and area estimates.

Experimental results

Research questions

• RQ1 How can decoy-rows be filtered under strict counter budgets to preserve Rowhammer detection?
• RQ2 Can in-DRAM DSAC maintain effective TRR under memory standard constraints like MR4?
• RQ3 How should TRR_TH adapt to changes in MPA_tREFIe to counter double-sided hammer?
• RQ4 What is the achievable improvement in Rowhammer mitigation (Maximum Disturbance) with DSAC?

Key findings

• DSAC achieves 49x lower Maximum Disturbance than the state-of-the-art counter-based algorithm.
• Time-Weighted Counting mitigates Passing Gate Effect by weighting long activations.
• DSAC filters out decoy-rows via stochastic replacement to preserve Rowhammer rows in the count table.
• Adaptive TRR_TH tied to MPA_tREFIe improves protection under MR4 scenarios.
• Architecture supports scalable counter budgets and still maintains effective TRR operation.