[Paper Review] Efficient Analog Circuits for Boolean Satisfiability

Xunzhao Yin, Behnam Sedighi+4 more|arXiv (Cornell University)|Jun 22, 2016

Quantum Computing Algorithms and Architecture26 references3 citations

TL;DR

This paper presents AC-SAT, a novel analog co-processor based on a continuous-time dynamical system (CTDS) that solves 3-SAT problems in nanoseconds using CMOS circuit design. SPICE simulations show up to 10⁴× speedup over state-of-the-art digital SAT solvers like MiniSat on hard 3-SAT instances with 50 variables and 212 clauses.

ABSTRACT

Efficient solutions to NP-complete problems would significantly benefit both science and industry. However, such problems are intractable on digital computers based on the von Neumann architecture, thus creating the need for alternative solutions to tackle such problems. Recently, a deterministic, continuous-time dynamical system (CTDS) was proposed (Nat.Phys. {\bf 7}(12), 966 (2011)) to solve a representative NP-complete problem, Boolean Satisfiability (SAT). This solver shows polynomial analog time-complexity on even the hardest benchmark $k$-SAT ($k \geq 3$) formulas, but at an energy cost through exponentially driven auxiliary variables. This paper presents a novel analog hardware SAT solver, AC-SAT, implementing the CTDS via incorporating novel, analog circuit design ideas. AC-SAT is intended to be used as a co-processor and is programmable for handling different problem specifications. It is especially effective for solving hard $k$-SAT problem instances that are challenging for algorithms running on digital machines. Furthermore, with its modular design, AC-SAT can readily be extended to solve larger size problems, while the size of the circuit grows linearly with the product of the number of variables and number of clauses. The circuit is designed and simulated based on a 32nm CMOS technology. SPICE simulation results show speedup factors of $\sim$10$^4$ on even the hardest 3-SAT problems, when compared with a state-of-the-art SAT solver on digital computers. As an example, for hard problems with $N=50$ variables and $M=212$ clauses, solutions are found within from a few $ns$ to a few hundred $ns$.

Motivation & Objective

• Address the intractability of NP-complete problems like Boolean Satisfiability (SAT) on von Neumann digital architectures.
• Overcome the limitations of digital SAT solvers, which face exponential time complexity on hard problem instances with high constraint density (M/N ≈ 4–5).
• Develop a hardware-efficient, programmable analog solution that exploits continuous-time dynamics to achieve polynomial-time analog computation.
• Design a scalable, modular analog circuit that grows linearly with problem size (N × M) and is suitable for integration as a co-processor.
• Demonstrate significant performance gains over digital counterparts by trading energy for computation time, particularly on hard SAT instances.

Proposed method

• Implement a continuous-time dynamical system (CTDS) proposed in prior work as an analog circuit, where SAT solutions emerge as attractors of the system's dynamics.
• Design three distinct circuit topologies to realize the auxiliary variable dynamics required by the CTDS, ensuring robustness and energy efficiency.
• Use a 32nm CMOS technology node for circuit design and SPICE simulation, enabling high-speed operation and scalability.
• Structure the AC-SAT architecture as a modular array of identical cells, each corresponding to a variable or clause, enabling extension to larger problems.
• Program the solver via initial conditions and external control signals, allowing mapping of different SAT instances without reconfiguration of the core circuit.
• Integrate programmable biasing and control logic to enable dynamic reconfiguration for different problem instances and initial conditions.

Experimental results

Research questions

• RQ1 Can a continuous-time dynamical system (CTDS) be effectively implemented in analog hardware to solve NP-complete problems like 3-SAT with sub-second runtime?
• RQ2 How does the performance of an analog SAT solver based on CTDS compare to state-of-the-art digital SAT solvers in terms of speed and energy efficiency?
• RQ3 To what extent can the modular and programmable design of the analog circuit scale to larger SAT problem instances?
• RQ4 How robust is the analog implementation to process variations and noise, given the theoretical sensitivity of dynamical systems?
• RQ5 Can the analog co-processor outperform digital ASICs and FPGA accelerators in solving hard SAT instances, especially those with high constraint density?

Key findings

• AC-SAT achieves solution times ranging from a few nanoseconds to a few hundred nanoseconds for hard 3-SAT instances with 50 variables and 212 clauses.
• SPICE simulations demonstrate a speedup of approximately 10⁴× over MiniSat running on a state-of-the-art digital processor for the hardest benchmark 3-SAT problems.
• The analog solver outperforms a projected digital ASIC implementation of MiniSat by over 600× in runtime, despite higher energy consumption.
• The CTDS-based analog system exhibits robustness to device variations and noise, as supported by theoretical and simulation results.
• The modular and programmable design allows for scalable extension to larger SAT problems, with circuit size growing linearly with the product of variables and clauses (O(N×M)).
• The system effectively trades energy cost for computation time, offering a viable path to accelerate time-sensitive, hard discrete optimization problems.