[Paper Review] Fast Equivalence-checking for Quantum Circuits

Shigeru Yamashita, Igor L. Markov|arXiv (Cornell University)|Sep 23, 2009

Quantum Computing Algorithms and Architecture7 citations

TL;DR

This paper proposes an adaptive, hybrid equivalence-checking methodology for quantum circuits that leverages reversible miters, SAT-based verification, and BDD techniques to achieve 3–4 orders of magnitude speedup over existing methods. By restructuring miter circuits to isolate and simplify reversible components and applying efficient SAT solvers to the remaining logic, the approach enables scalable verification of large-scale quantum circuits such as those in Shor’s algorithm.

ABSTRACT

We perform formal verification of quantum circuits by integrating several techniques specialized to particular classes of circuits. Our verification methodology is based on the new notion of a reversible miter that allows one to leverage existing techniques for circuit simplification of quantum circuits. For reversible circuits which arise as runtime bottlenecks of key quantum algorithms, we develop several verification techniques and empirically compare them. We also combine existing quantum verification tools with the use of SAT-solvers. Experiments with circuits for Shor's number-factoring algorithm, containing thousands of gates, show improvements in efficiency by 3-4 orders of magnitude.

Motivation & Objective

• To address the scalability challenge in verifying large-scale quantum circuits, especially those arising from physical architecture mappings.
• To overcome the inefficiency of traditional BDD- and simulator-based methods for equivalence-checking quantum circuits with thousands of gates.
• To develop a hybrid verification methodology that adapts to the structural and functional heterogeneity of quantum circuit modules.
• To enable practical formal verification of quantum circuits used in key algorithms like Shor’s number factoring, which rely heavily on reversible modular exponentiation circuits.

Proposed method

• Introduces the concept of a reversible miter, a quantum circuit construction analogous to digital miter circuits, to enable equivalence-checking between two quantum circuits.
• Applies iterative circuit simplification techniques to reduce the size and complexity of the miter before verification.
• Employs SAT-based combinational equivalence-checking (via ABC’s cec tool) on the simplified reversible prefix of the miter, leveraging the efficiency of classical logic verification.
• Uses lightweight quantum simulation (QuIDDPro) to validate the functionality of remaining properly-quantum gates, ensuring they are not entangled or superposed in a way that invalidates classical equivalence.
• Integrates BDD-based symbolic simulation and SAT-based checking in a hybrid pipeline, selecting the most appropriate technique per circuit module.
• Applies gate reordering and transformation (e.g., decomposing SWAPs into CNOTs) to expose structural similarities and enable cancellation of equivalent gate pairs.

Experimental results

Research questions

• RQ1 Can reversible miters significantly reduce the complexity of quantum circuit equivalence-checking by isolating classical reversible logic?
• RQ2 How does SAT-based equivalence-checking compare to BDD- and simulator-based methods for verifying large quantum circuits?
• RQ3 To what extent can circuit simplification and gate reordering improve the performance of equivalence-checking tools on quantum circuits?
• RQ4 Can hybrid verification techniques combining SAT, BDD, and lightweight simulation outperform monolithic quantum simulation on circuits with mixed reversible and properly-quantum components?
• RQ5 What is the performance gain of the proposed adaptive methodology on real-world quantum circuits such as those in Shor’s algorithm?

Key findings

• The proposed method achieved verification of Shor’s number-factoring circuits with thousands of gates in under seven seconds, while the baseline QuIDDPro simulator failed to complete within ten hours.
• The integration of SAT-based equivalence-checking (via ABC’s cec) with reversible miters and simplification reduced verification time by 3–4 orders of magnitude compared to existing quantum simulation tools.
• SAT-based verification outperformed BDD-based techniques for the same task, contrary to prior assumptions, especially when applied to simplified reversible prefixes.
• The use of reversible miters enabled effective cancellation of equivalent gate pairs and structural optimization, particularly after SWAP gate decomposition and reordering.
• Lightweight simulation of properly-quantum components was sufficient to validate functionality, avoiding the need for full-scale quantum simulation in most cases.
• The adaptive methodology successfully verified a Grover oracle circuit with a multiplier-based predicate, demonstrating robustness on complex, real-world quantum circuit transformations.