[Paper Review] FERS-5200: a distributed Front-End Readout System for multidetector arrays

M. Venaruzzo, Andrea Abba+2 more|arXiv (Cornell University)|Oct 29, 2020

Advanced Semiconductor Detectors and Materials4 citations

TL;DR

FERS-5200 is a scalable, distributed front-end readout platform for large detector arrays, using optical TDlink for daisy-chaining up to 128 FERS units (8,192 channels) with synchronized data acquisition, low-jitter timing, and support for multiple detector types via interchangeable ASIC-based front-ends. The A5202 card, based on the CITIROC-1A ASIC, achieves sub-1% ADC non-linearity and single photoelectron sensitivity in high-gain mode, enabling high-precision spectroscopy and timing in nuclear and particle physics experiments.

ABSTRACT

The FERS-5200 is the new CAEN Front-End Readout System for large detector arrays. It consists in a compact, distributed and easy-deployable solution integrating front-end based on ASICs, A/D conversion, data processing, synchronization and readout. Using the appropriate Front-End the solution perfectly fits a wide range of detectors such as SiPMs, multianode PMTs, GEMs, Silicon Strip detectors, Wire Chambers, Gas Tubes, etc. The first member of the FERS family is the unit A5202, a 64 channel readout card for SiPMs, based on the CITIROC ASIC by Weeroc SaS. The Concentrator board DT5215 can manage the readout of up to 128 cards at once, that is 8192 readout channels in case of the A5202.

Motivation & Objective

• To address the growing need for scalable, cost-effective, and low-jitter readout systems for large-scale detector arrays in nuclear and particle physics experiments.
• To develop a modular front-end platform that supports diverse detector types—such as SiPMs, MA-PMTs, GEMs, and silicon strip detectors—through interchangeable ASIC-based front-ends.
• To enable seamless transition from small-scale evaluation systems to large-scale installations via a unified hardware and data acquisition (DAQ) architecture.
• To achieve high channel density, low power consumption, and precise synchronization across thousands of channels using optical TDlink communication.
• To validate system performance with quantitative characterization of ADC and ToT non-linearity, and to demonstrate single photoelectron sensitivity.

Proposed method

• The FERS-5200 platform uses a distributed architecture where each FERS unit is a compact 64-channel card housing ASIC-based front-end, ADC, TDC, FPGA, and optical I/O, enabling independent operation or networked daisy-chaining.
• A high-speed 6.25 Gbit/s optical TDlink protocol synchronizes up to 16 FERS units in a daisy chain, carrying clock, control commands, triggers, and data, with a readout bandwidth exceeding 100 MB/s.
• The Concentrator Board DT5215 manages up to 128 FERS cards via eight TDlinks, enabling a scalable FERSnet architecture with centralized control and data acquisition over 1/10 GbE or USB 3.0.
• The A5202 card uses the CITIROC-1A ASIC for SiPM readout, featuring two programmable variable-gain preamplifiers (low/high gain), fast and slow discriminators, and a 12-bit flash ADC with time-over-threshold (ToT) measurement.
• Synchronization is achieved via a shared reference clock and auto-synchronization procedures over the TDlink, with minimal jitter and deterministic timing for multi-channel applications.
• System performance is evaluated through charge injection tests using pulsed signals and LED excitation of SiPMs, with ADC and ToT non-linearity analyzed via linear fitting and RMS deviation in photoelectrons.

Experimental results

Research questions

• RQ1 Can a distributed front-end readout system achieve sub-1% ADC non-linearity across a wide dynamic range in both low- and high-gain modes?
• RQ2 What is the achievable energy resolution and single photoelectron sensitivity in high-gain mode using the CITIROC-1A ASIC on the A5202 card?
• RQ3 How does the TDlink protocol enable reliable, low-jitter synchronization and data transfer across up to 128 FERS units in a scalable network?
• RQ4 To what extent can the FERS-5200 platform support diverse detector types through interchangeable front-end ASICs or hybrid configurations?
• RQ5 What is the non-linearity of the time-over-threshold (ToT) measurement in low-gain mode, and how does it compare to the ADC response?

Key findings

• The ADC non-linearity of the A5202 card is within 0.5% to 1.5% across both low-gain and high-gain modes, with a linear fit RMS of 6.8 p.e. in low-gain and 0.34 p.e. in high-gain mode.
• The ToT non-linearity in low-gain mode is within 10%, with a linear fit RMS of 47.2 p.e., indicating moderate energy resolution for timing and charge measurements.
• Single photoelectron sensitivity is achievable in high-gain mode, with a measured RMS of 0.34 p.e. for the ADC, demonstrating sub-1% non-linearity at the single p.e. level.
• The TDlink protocol supports a readout bandwidth exceeding 100 MB/s and enables daisy-chaining of up to 16 FERS units per link, with the DT5215 concentrator supporting up to 128 cards (8,192 channels) in a single network.
• The system achieves stable synchronization across multiple units, with auto-synchronization procedures introducing only minor, unpredictable delays due to high-priority control packets.
• The platform enables a seamless transition from small-scale evaluation to large-scale installations, with identical DAQ and hardware architecture across all configurations.