[Paper Review] MUQUT: Multi-Constraint Quantum Circuit Mapping on Noisy Intermediate-Scale Quantum Computers

Debjyoti Bhattacharjee, Abdullah Ash Saki+3 more|arXiv (Cornell University)|Nov 16, 2019

Quantum Computing Algorithms and Architecture18 references4 citations

TL;DR

MUQUT proposes a multi-constraint quantum circuit mapping framework for NISQ devices that jointly optimizes for nearest-neighbor (NN) connectivity, gate fidelity, logical depth, and gate count. By integrating topology-aware mapping with noise-aware qubit placement using a multi-tier heuristic and ILP-based approach, it achieves up to 6.76× average fidelity improvement on IBMQ16 and 3.37× on average across 10 benchmarks, with 1.96× improvement on QFT-5 alone.

ABSTRACT

Rapid advancement in the domain of quantum technologies has opened up researchers to the real possibility of experimenting with quantum circuits and simulating small-scale quantum programs. Nevertheless, the quality of currently available qubits and environmental noise poses a challenge in the smooth execution of the quantum circuits. Therefore, efficient design automation flows for mapping a given algorithm to the Noisy Intermediate Scale Quantum (NISQ) computer becomes of utmost importance. State-of-the-art quantum design automation tools are primarily focused on reducing logical depth, gate count and qubit count with the recent emphasis on topology-aware (nearest-neighbor compliance) mapping. In this work, we extend the technology mapping flows to simultaneously consider the topology and gate fidelity constraints while keeping logical depth and gate count as optimization objectives. We provide a comprehensive problem formulation and multi-tier approach towards solving it. The proposed automation flow is compatible with commercial quantum computers, such as IBM QX and Rigetti. Our simulation results over 10 quantum circuit benchmarks show that the fidelity of the circuit can be improved up to 3.37X with an average improvement of 1.87X.

Motivation & Objective

• To address the gap in existing quantum design flows that treat topology and fidelity constraints separately, rather than jointly optimizing them.
• To develop a scalable, multi-tier technology mapping flow compatible with commercial NISQ architectures like IBM QX and Rigetti.
• To improve quantum circuit fidelity by simultaneously minimizing gate count and logical depth while enforcing nearest-neighbor compliance and leveraging qubit-specific error rates.
• To provide a comprehensive design space exploration framework that supports various topology graphs, window sizes, and noise-aware mapping strategies.

Proposed method

• Formulates a multi-constraint quantum circuit mapping problem that jointly optimizes for nearest-neighbor compliance, gate count, logical depth, and qubit-specific gate fidelity.
• Employs a multi-tier approach combining integer linear programming (ILP) for optimal sub-problems and heuristic techniques for scalability in large circuits.
• Uses a windowed topology solver with variable window sizes (w = 1, 2, 4, 6) to explore multi-level optimizations for reducing CNOT and other native gate counts.
• Integrates noise-aware qubit mapping by modeling qubit-to-qubit error rates and selecting placements that minimize cumulative error across the circuit.
• Validates the flow on 10 quantum circuit benchmarks across IBMQ16 and Rigetti 16-qubit architectures using realistic error models and native gate sets.
• Leverages Gurobi 8 as the ILP solver for optimal sub-solutions in gate reduction and mapping, while maintaining compatibility with commercial quantum hardware.

Experimental results

Research questions

• RQ1 How can topology and gate fidelity constraints be jointly optimized in quantum circuit mapping for NISQ devices?
• RQ2 What is the impact of varying window size in a multi-level topology solver on gate count and circuit fidelity?
• RQ3 To what extent can noise-aware qubit placement improve circuit fidelity compared to random or topology-only mappings?
• RQ4 How does the proposed flow scale across different quantum hardware architectures, such as IBM QX and Rigetti, with distinct native gate sets and connectivity?
• RQ5 Can a unified framework simultaneously reduce logical depth, gate count, and error accumulation while ensuring nearest-neighbor compliance?

Key findings

• The proposed MUQUT flow achieves up to 6.76× improvement in circuit fidelity on the IBMQ16 architecture, with the highest gain observed on the QFT-5 benchmark.
• On average across 10 benchmarks, the fidelity improvement is 1.87×, with a 1.96× improvement specifically on the QFT-5 benchmark due to its high gate count.
• The use of a noise-aware mapping step reduces the number of CNOT gates and improves fidelity, especially when combined with gate-reduction techniques.
• Larger window sizes (w = 4, 6) in the topology solver reduce total gate count more effectively, though at the cost of increased runtime.
• The flow demonstrates compatibility with both IBM QX (CNOT-based) and Rigetti (CZ-based) architectures, showing consistent fidelity improvements across different native gate sets.
• Fidelity improvements are most significant in circuits with high gate counts, such as QFT-5, confirming the inverse relationship between gate count and fidelity.