[Paper Review] Novel BCD Adders and Their Reversible Logic Implementation for IEEE 754r Format

Himanshu Thapliyal, Saurabh Kotiyal+1 more|ArXiv.org|Mar 22, 2006

Quantum Computing Algorithms and Architecture5 references4 citations

TL;DR

This paper proposes two novel BCD adders—carry skip and carry look-ahead—optimized for the IEEE 754r decimal floating-point standard. It implements these using reversible logic, introducing a new TS-3 gate and leveraging the TSG gate, achieving significant reductions in reversible gate count and garbage outputs compared to prior designs, thus enabling efficient decimal arithmetic in quantum and low-power computing systems.

ABSTRACT

IEEE 754r is the ongoing revision to the IEEE 754 floating point standard and a major enhancement to the standard is the addition of decimal format. This paper proposes two novel BCD adders called carry skip and carry look-ahead BCD adders respectively. Furthermore, in the recent years, reversible logic has emerged as a promising technology having its applications in low power CMOS, quantum computing, nanotechnology, and optical computing. It is not possible to realize quantum computing without reversible logic. Thus, this paper also paper provides the reversible logic implementation of the conventional BCD adder as the well as the proposed Carry Skip BCD adder using a recently proposed TSG gate. Furthermore, a new reversible gate called TS-3 is also being proposed and it has been shown that the proposed reversible logic implementation of the BCD Adders is much better compared to recently proposed one, in terms of number of reversible gates used and garbage outputs produced. The reversible BCD circuits designed and proposed here form the basis of the decimal ALU of a primitive quantum CPU.

Motivation & Objective

• To address the need for efficient decimal arithmetic in emerging IEEE 754r standard for floating-point computation.
• To design high-performance BCD adders tailored for decimal floating-point operations in next-generation processors.
• To implement BCD adders using reversible logic to support low-power and quantum-computing applications.
• To minimize resource overhead by reducing the number of reversible gates and garbage outputs in BCD adder circuits.

Proposed method

• Designing a carry skip BCD adder that reduces propagation delay by skipping groups of digits with no carry-in.
• Implementing a carry look-ahead BCD adder to further accelerate carry computation using generate and propagate signals.
• Using the recently proposed TSG gate as the foundational reversible logic element for constructing BCD adder components.
• Proposing a new reversible gate, TS-3, optimized for BCD addition logic with improved area and power efficiency.
• Mapping conventional and novel BCD adders onto reversible logic circuits using TSG and TS-3 gates.
• Evaluating circuit complexity in terms of gate count and garbage outputs to demonstrate superiority over existing designs.

Experimental results

Research questions

• RQ1 How can BCD adders be optimized for faster computation in the context of the IEEE 754r decimal floating-point standard?
• RQ2 What reversible logic design techniques can minimize gate count and garbage outputs in BCD adders?
• RQ3 Can a new reversible gate (TS-3) outperform existing reversible gates in BCD adder implementations?
• RQ4 How does the proposed carry skip and carry look-ahead BCD adder architecture compare to conventional BCD adders in terms of efficiency?
• RQ5 To what extent can reversible logic implementations of BCD adders support the development of a decimal ALU in a quantum CPU?

Key findings

• The proposed carry skip and carry look-ahead BCD adders achieve reduced propagation delay compared to conventional BCD adders.
• The reversible logic implementation using the TSG gate and the new TS-3 gate results in fewer reversible gates than previous designs.
• The number of garbage outputs is significantly reduced in the proposed reversible BCD adders, enhancing efficiency.
• The TS-3 gate enables more compact and efficient logic synthesis for BCD addition operations.
• The overall reversible circuit design demonstrates superior performance in terms of gate count and garbage output compared to recently published implementations.
• The proposed circuits are suitable as building blocks for a decimal ALU in a primitive quantum CPU.