[Paper Review] Parity Quantum Optimization: Compiler

Kilian Ender, Roeland ter Hoeven+3 more|arXiv (Cornell University)|May 13, 2021

Quantum Computing Algorithms and Architecture4 citations

TL;DR

This paper introduces a parity quantum optimization compiler that directly encodes higher-order constrained binary optimization (HCBO) problems with arbitrary k-body interactions and side constraints onto planar quantum chips, bypassing QUBO conversion. By generalizing the LHZ mapping to hypergraphs and open cycles, it enables full parallelization, reduces qubit overhead from O(N²) to O(K), and supports native implementation of product constraints without auxiliary qubits.

ABSTRACT

We introduce parity quantum optimization with the aim of solving optimization problems consisting of arbitrary $k$-body interactions and side conditions using planar quantum chip architectures. The method introduces a decomposition of the problem graph with arbitrary $k$-body terms using generalized closed cycles of a hypergraph. Side conditions of the optimization problem in form of hard constraints can be included as open cycles containing the terms involved in the side conditions. The generalized parity mapping thus circumvents the need to translate optimization problems to a quadratic unconstrained binary optimization problem (QUBO) and allows for the direct encoding of higher-order constrained binary optimization problems (HCBO) on a square lattice and full parallelizability of gates.

Motivation & Objective

• To address the inefficiency of mapping higher-order optimization problems to QUBO, which requires extensive auxiliary qubit overhead.
• To enable direct encoding of arbitrary k-body interactions and side constraints on square-lattice quantum hardware without QUBO decomposition.
• To develop a compiler that maps HCBO problems to physical layouts with minimal qubit usage and maximal gate parallelization.
• To generalize the LHZ mapping to hypergraphs and open cycles for handling product constraints without additional resources.
• To provide a scalable, hardware-optimized framework for digital quantum algorithms on current and near-term devices.

Proposed method

• The parity transformation maps k-body logical spin products to single parity qubits, reducing the number of required physical qubits from O(N²) to O(K), where K is the number of terms in the Hamiltonian.
• Generalized closed cycles in a hypergraph representation replace the original all-to-all connectivity, enabling local couplings on a 2D square lattice.
• Open cycles are introduced to encode side conditions as product constraints, with no additional qubit cost.
• The compiler uses CNOT-based tree structures to implement code space projectors, allowing flexible and parallelizable physical layout generation.
• The method supports full parallelization of gates by arranging plaquettes and projectors in a way that maximizes concurrent gate operations.
• The approach avoids SWAP gates and maintains system-size-independent circuit depth, crucial for minimizing error accumulation in near-term devices.

Figure 1: (a) An unconstrained optimization problem is represented by a graph consisting of spins (circles) and edges (black lines). The parity construction is based on finding closed loops of length 3 and 4, e.g., the red triangle connecting spins 1,2 and 6 is a closed loop of length 3. The compile

Experimental results

Research questions

• RQ1 Can higher-order interactions in optimization problems be encoded directly on planar quantum architectures without QUBO decomposition?
• RQ2 How can side constraints, particularly product constraints, be encoded without introducing auxiliary qubits or increasing qubit overhead?
• RQ3 What is the minimal qubit and gate overhead required to implement arbitrary k-body interactions and constraints on a square lattice?
• RQ4 How can the layout of parity-encoded circuits be optimized for maximum gate parallelization and minimal circuit depth?
• RQ5 Can the generalized parity mapping be extended to support general sum constraints while preserving resource efficiency?

Key findings

• The parity compiler reduces qubit overhead from O(N²) to O(K), where K is the number of k-body terms, significantly improving resource efficiency for dense optimization problems.
• Product constraints are encoded via open cycles in the hypergraph, requiring no additional qubits or auxiliary variables.
• The resulting circuits are fully parallelizable, enabling system-size-independent circuit depth, which is critical for error resilience in near-term quantum devices.
• The method avoids the need for SWAP gates, reducing gate count and circuit depth, especially beneficial for high-order interaction graphs.
• The compiler-generated layouts support arbitrary shapes of CNOT chains and projectors, enabling flexible optimization of physical layout for performance and error mitigation.
• Benchmarking in Ref. [28] confirms that this architecture reduces resource requirements and improves gate efficiency for quantum approximate optimization algorithms.