[Paper Review] A Clock Synchronizer for Repeaterless Low Swing On-Chip Links

Naveen Kadayinti, Maryam Shojaei Baghini+1 more|arXiv (Cornell University)|Oct 14, 2015

Advancements in PLL and VCO Technologies9 references3 citations

TL;DR

This paper presents a delay-locked loop (DLL)-based clock synchronizer for repeaterless low-swing on-chip interconnects that uses a phase detector to lock the sampling clock to the eye center and an analog voltage-controlled delay for fine-tuning. The design achieves 1.4 mW at 1.3 Gbps in 130 nm CMOS and 1.5 mW at 4 Gbps in 65 nm CMOS, with data transferred to the receiver domain in ≤3 cycles using a mesochronous synchronizer.

ABSTRACT

A clock synchronizing circuit for repeaterless low swing interconnects is presented in this paper. The circuit uses a delay locked loop (DLL) to generate multiple phases of the clock, of which the one closest to the center of the eye is picked by a phase detector loop. The picked phase is then further fine tuned by an analog voltage controlled delay to position the sampling clock at the center of the eye. A clock domain transfer circuit then transfers the sampled data to the receiver clock domain with a maximum latency of three clock cycles. The proposed synchronizer has been designed and fabricated in 130 nm UMC MM CMOS technology. The circuit consumes 1.4 mW from a 1.2 V supply at a data rate of 1.3 Gbps. Further, the proposed synchronizer has been designed and simulated in TSMC 65 nm CMOS technology. Post layout simulations show that the synchronizer consumes 1.5 mW from a 1 V supply, at a data rate of 4 Gbps in this technology.

Motivation & Objective

• To address the lack of effective clock synchronization in repeaterless low-swing on-chip interconnects, which suffer from high interconnect delay and phase misalignment.
• To enable high-speed, low-power data recovery without repeaters by precisely aligning the sampling clock to the eye center.
• To minimize data transfer latency between clock domains by designing a synchronizer with maximum latency of three cycles.
• To overcome the risk of false locking in phase detectors by ensuring robust convergence to the correct eye center phase.

Proposed method

• A delay-locked loop (DLL) generates multiple clock phases, with the phase closest to the eye center selected by a phase detector.
• An analog voltage-controlled delay fine-tunes the selected phase to precisely position the sampling clock at the eye center.
• The Alexander phase detector samples data at three points per bit period to detect phase error between clock and data, using XOR-based UP/DN signals.
• A charge pump integrates the phase error signal to control the delay line, forming a negative feedback loop for stable locking.
• A clock domain transfer circuit synchronizes the sampled data to the receiver clock domain with a maximum latency of three cycles.
• The design is fabricated in 130 nm UMC CMOS and simulated in TSMC 65 nm CMOS for performance validation.

Experimental results

Research questions

• RQ1 How can clock synchronization be achieved in repeaterless low-swing on-chip interconnects without relying on repeaters?
• RQ2 What techniques can ensure precise sampling at the eye center despite process and process variation?
• RQ3 How can false locking in phase detectors be mitigated, especially when the clock is exactly π radians offset from the eye center?
• RQ4 What is the maximum data transfer latency between clock domains in a mesochronous synchronizer for such links?
• RQ5 How does the proposed design perform in terms of power consumption and data rate across different process technologies?

Key findings

• The proposed clock synchronizer consumes 1.4 mW from a 1.2 V supply at 1.3 Gbps in 130 nm UMC CMOS technology.
• Post-layout simulations show 1.5 mW power consumption at 4 Gbps in 65 nm TSMC CMOS technology with a 1 V supply.
• The phase detector can falsely lock to the wrong edge when the clock is π radians offset from the eye center and data has 50% activity, but noise and data randomness eventually resolve this.
• False locking is unlikely to persist after initial lock, as the system state stabilizes near the correct phase once achieved.
• The clock domain transfer circuit ensures data is transferred to the receiver clock domain within a maximum of three cycles.
• The design successfully leverages low-swing interconnects for high-speed, low-power communication without repeaters.