[Paper Review] A Survey on Approximate Multiplier Designs for Energy Efficiency: From Algorithms to Circuits

Ying Wu, Chuangtao Chen+7 more|arXiv (Cornell University)|Jan 28, 2023

Low-power high-performance VLSI design4 citations

TL;DR

This survey provides a comprehensive analysis of approximate multiplier designs for energy efficiency in IoT edge devices, spanning algorithms, architectures, and circuits. It evaluates techniques like logarithmic, linearization-based, and hybrid approximations, showing that linearization offers high energy savings with minimal error, while circuit-level optimizations such as gate pruning and voltage scaling further enhance efficiency with controlled accuracy loss in applications like machine learning.

ABSTRACT

Given the stringent requirements of energy efficiency for Internet-of-Things edge devices, approximate multipliers, as a basic component of many processors and accelerators, have been constantly proposed and studied for decades, especially in error-resilient applications. The computation error and energy efficiency largely depend on how and where the approximation is introduced into a design. Thus, this article aims to provide a comprehensive review of the approximation techniques in multiplier designs ranging from algorithms and architectures to circuits. We have implemented representative approximate multiplier designs in each category to understand the impact of the design techniques on accuracy and efficiency. The designs can then be effectively deployed in high-level applications, such as machine learning, to gain energy efficiency at the cost of slight accuracy loss.

Motivation & Objective

• To provide a systematic review of approximate multiplier techniques across algorithmic, architectural, and circuit levels for energy-constrained IoT edge devices.
• To evaluate the trade-offs between accuracy, energy efficiency, and hardware cost in various approximation techniques.
• To identify design space synergies between approximate algorithms and underlying multiplier circuits for optimal performance.
• To guide application-specific selection of approximate multipliers by analyzing error metrics and sensitivity to synthesis modes.

Proposed method

• Categorizing approximate multiplier techniques into algorithmic (logarithmic, linearization, hybrid), architectural (truncation, partial product alteration, approximate compressors), and circuit-level (gate pruning, Boolean rewriting, voltage scaling) approaches.
• Implementing representative designs from each category to evaluate accuracy and energy efficiency using both generic benchmarks and machine learning workloads.
• Analyzing error characteristics such as mean error, maximum relative error (MRED), and normalized mean error distance (NMED) across different approximation levels.
• Investigating the interplay between algorithmic approximation and circuit-level implementation, particularly in error distribution and bias control.
• Evaluating the impact of synthesis modes on circuit area and performance to assess real-world deployment viability.
• Using application-level evaluation in machine learning and image processing to validate energy savings and accuracy trade-offs.

Experimental results

Research questions

• RQ1 How do different algorithmic approaches—logarithmic, linearization-based, and hybrid—compare in terms of energy efficiency and error characteristics?
• RQ2 What is the impact of architectural-level truncation and partial product manipulation on accuracy and hardware cost in approximate multipliers?
• RQ3 How do circuit-level techniques like gate pruning and voltage scaling affect energy efficiency and error distribution?
• RQ4 What are the key factors influencing the selection of an approximate multiplier for specific applications like machine learning?
• RQ5 How does the choice of synthesis mode affect the performance and area of approximate multiplier designs?

Key findings

• Linearization-based approximation achieves substantial energy and area savings with negligible errors and zero-mean error distribution, making it highly suitable for error-tolerant applications.
• Logarithmic-based multipliers offer significant hardware savings but suffer from one-sided errors; iterative versions reduce bias at the cost of increased hardware complexity.
• Truncation-based architectural techniques reduce area and delay but can introduce large relative errors for small operands, especially in fixed-point arithmetic.
• The use of approximate compressors in the partial product reduction tree improves energy efficiency, though optimal placement and ordering remain challenging problems.
• Circuit-level optimizations such as gate pruning and voltage scaling reduce energy consumption effectively, but timing violations on critical paths (MSBs) can lead to non-negligible errors.
• Application-level evaluations show that approximation aggressiveness, error bias, and fitness to the algorithm significantly influence performance, indicating that selection must go beyond basic error metrics like MRED and NMED.