[Paper Review] Development of A 16:1 serializer for data transmission at 5 Gbps

S. Hou, Z. Liang+7 more|arXiv (Cornell University)|Jan 1, 2009

Advancements in PLL and VCO Technologies12 references3 citations

TL;DR

This paper presents a 16:1 serializer ASIC designed for 5 Gbps data transmission in radiation environments typical of high-energy physics experiments. Fabricated using 0.25 µm silicon-on-sapphire CMOS, it achieves 500 mW power consumption, 54 ps peak-to-peak deterministic jitter, and less than 3 ps RMS random jitter, enabling high-speed, low-power optical links for LHC detector upgrades.

ABSTRACT

Radiation tolerant, high speed and low power serializer ASIC is critical for optical link systems in particle physics experiments. Based on a commercial 0.25 um silicon-on-sapphire CMOS technology, we design a 16:1 serializer with 5 Gbps serial data rate. This ASIC has been submitted for fabrication. The post-layout simulation indicates the deterministic jitter is 54 ps (pk-pk) and random jitter is 3 ps (rms). The power consumption of the serializer is 500 mW. The design details and post layout simulation results are presented in this paper.

Motivation & Objective

• Address the need for high-speed, low-power, radiation-tolerant serializers in next-generation particle physics experiments.
• Overcome limitations of existing GOL and G-link chips in power consumption and data rate for LHC super-upgrade requirements.
• Enable 100 Gbps optical data links with minimal power budget per front-end board.
• Leverage 0.25 µm silicon-on-sapphire (SoS) CMOS technology for improved radiation tolerance and speed.
• Design a high-speed serializer with low jitter and robustness against single-event effects (SEE).

Proposed method

• Employ a 16:1 multiplexer architecture with four cascaded 2:1 multiplexer stages, using static D-flip-flops with symmetrical complementary clock signals for high-speed operation.
• Implement a phase-locked loop (PLL) with a voltage-controlled oscillator (VCO), charge pump, and low-pass filter to generate precise, phase-locked clock signals at 312.5 MHz, 625 MHz, 1.25 GHz, and 2.5 GHz.
• Use a current-mode logic (CML) driver with four stages and 20 mA bias current to drive 50 Ω transmission lines, ensuring signal integrity at 5 Gbps.
• Integrate LVDS receivers to convert differential input signals to CMOS levels for processing.
• Apply radiation-hardening techniques, including large transistor sizes and static D-flip-flops, to enhance immunity to single-event effects (SEE).
• Separate power and ground networks for the multiplexer and PLL to minimize noise coupling and jitter.

Experimental results

Research questions

• RQ1 Can a 16:1 serializer achieve 5 Gbps data rate while consuming less than 500 mW in a radiation-tolerant environment?
• RQ2 What is the achievable jitter performance (deterministic and random) of a 5 Gbps serializer in 0.25 µm SoS CMOS?
• RQ3 How does bonding wire inductance affect the bandwidth and signal integrity of the CML driver output?
• RQ4 Can the use of symmetrical complementary clock signals in D-flip-flops enable operation beyond 2 GHz in high-speed multiplexer stages?
• RQ5 To what extent can power consumption be reduced by sharing a single PLL across multiple serializers in future designs?

Key findings

• The serializer achieves a 5 Gbps serial data rate with a total power consumption of 507 mW, including 238 mW for the 16:1 multiplexer, 173 mW for the PLL, and 96 mW for the CML driver.
• Post-layout simulation shows a deterministic jitter of 54 ps (pk-pk), indicating excellent timing stability.
• Random jitter is estimated at less than 3 ps (RMS), primarily from VCO phase noise, demonstrating low timing jitter.
• The CML driver achieves a 3 dB bandwidth of 5.5 GHz with 1 mm bonding wires, degrading to 3.6 GHz with 5 mm wires, highlighting the need for short interconnects.
• The eye diagram simulation shows a clear eye opening with a peak-to-peak output amplitude exceeding 400 mV at 5 Gbps, confirming signal integrity.
• The design is fabricated using 0.25 µm SoS CMOS, which provides high-speed operation (fT = 90 GHz) and enhanced radiation tolerance for particle physics applications.