[Paper Review] Low Latency Neural Networks using Heterogenous Resources on FPGA for the Belle II Trigger

S. Baehr, S. Mccarney+6 more|arXiv (Cornell University)|Oct 30, 2019

Particle Detector Development and Performance8 references4 citations

TL;DR

This paper presents an optimized FPGA-based neural z-Vertex trigger for the Belle II experiment that reduces DSP resource usage by 40% through time-multiplexed scheduling of multiply-accumulate (MAC) operations and balanced utilization of SRAM-LUTs and DSPs. The approach enables two parallel neural networks to run within the 5µs latency budget, improving throughput while maintaining timing closure on a Virtex UltraScale FPGA.

ABSTRACT

One of the major components of the Belle II trigger system is the neural network trigger. Its task is to estimate the z-Vertex particle tracks observed in the experiments drift chamber. The trigger is implemented on FPGAs to ensure exibility during operation and leverage their IO capabilities. Meanwhile the implementation has to estimate the vertex in a few hundred nanoseconds to fulfil the requirements of the experiment. A first version of that trigger was operational during the first collisions. While it was able to estimate the vertex, it had some drawbacks regarding the possible throughput and timing closure. These are the focus of this work, which modifies the original design to allow two networks running in parallel and less routing congestion. We conducted a rescheduling of multiply and accumulate which are the basic operations in such networks. While the original design tried to parallelize as much as possible, the rescheduling tries to reduce the number of parallel data transmission by reusing processing modules. This way resource consumption was reduced by 40% for DSPs. To further increase the throughput by operating an additional network in parallel, we investigated the balanced use of SRAM-LUTs and DSPs for multiply and accumulate operations. With the found balancing ratio the trigger is able to operate two neural networks in parallel on the targeted FPGA within the required latency.

Motivation & Objective

• Address resource congestion and throughput limitations in the existing FPGA-based neural z-Vertex trigger for Belle II.
• Reduce DSP resource consumption while maintaining 5µs latency and 31.75 MHz throughput requirements.
• Enable operation of two parallel neural networks on a single FPGA by optimizing resource balancing between SRAM-LUTs and DSPs.
• Improve routing efficiency and timing closure through re-scheduling of MAC operations across clock cycles.
• Develop a scalable solution for future upgrades requiring higher track processing capacity.

Proposed method

• Rescheduled multiply-accumulate (MAC) operations across multiple clock cycles to reduce parallel data transmission and reuse processing units.
• Implemented time-multiplexed execution of MACs within a single neuron and across neurons to minimize resource demand.
• Balanced MAC computation between DSPs and SRAM-LUTs, using 40% in LUTs and 60% in DSPs to avoid resource bottlenecks.
• Interleaved and pipelined layer execution to reduce latency and improve resource utilization without exceeding the 5µs deadline.
• Used a controller to manage multiplexer routing and data flow across clock cycles in the time-multiplexed design.
• Evaluated designs on a Virtex UltraScale XCVU080 FPGA using resource utilization and timing analysis.

Experimental results

Research questions

• RQ1 How can MAC operations in a neural network trigger be rescheduled to reduce DSP resource usage without increasing latency?
• RQ2 What is the optimal balance between SRAM-LUTs and DSPs for implementing MAC units in a low-latency FPGA design?
• RQ3 Can two parallel neural networks be executed within the 5µs latency budget using heterogeneous resource utilization?
• RQ4 How does time-multiplexing of MACs affect routing congestion and overall design routability?
• RQ5 To what extent can resource consumption be reduced while maintaining the required 31.75 MHz throughput and 5µs latency?

Key findings

• Time-multiplexing of MAC operations reduced DSP usage by 40% compared to the original parallel design, achieving 297 DSP-based MAC units.
• The heterogeneous implementation used 44% of DSPs and 30% of SRAM-LUTs, compared to 68% DSP and 17% LUTs in the DSP-only approach.
• The balanced use of SRAM-LUTs and DSPs reduced routing congestion by reusing input values instead of routing them in parallel.
• The design achieved a maximum frequency of 127 MHz, satisfying the 5µs latency constraint despite increased pipelining.
• The optimized design supports two parallel neural networks on the same FPGA, enabling higher throughput for future upgrades.
• The method reduced resource pressure on critical paths, improving timing closure and design stability on the XCVU080 FPGA.