[Paper Review] The Analog Front-end for the LGAD Based Precision Timing Application in CMS ETL

Quan Sun, S. Dogra+21 more|arXiv (Cornell University)|Dec 28, 2020

Particle Detector Development and Performance9 references6 citations

TL;DR

This paper presents ETROC0, the first 65 nm CMOS mini-ASIC prototype for the CMS Endcap Timing Layer (ETL), featuring an analog front-end with preamplifier and discriminator stages optimized for Low Gain Avalanche Detectors (LGADs). Designed to achieve 40–50 ps time resolution per hit, beam tests demonstrated 33 ps resolution from preamplifier waveforms and 41 ps from discriminator pulses, with no performance degradation after 100 MRad total ionizing dose.

ABSTRACT

The analog front-end for the Low Gain Avalanche Detector (LGAD) based precision timing application in the CMS Endcap Timing Layer (ETL) has been prototyped in a 65 nm CMOS mini-ASIC named ETROC0. Serving as the very first prototype of ETL readout chip (ETROC), ETROC0 aims to study and demonstrate the performance of the analog frontend, with the goal to achieve 40 to 50 ps time resolution per hit with LGAD (therefore reach about 30ps per track with two detector-layer hits per track). ETROC0 consists of preamplifier and discriminator stages, which amplifies the LGAD signal and generates digital pulses containing time of arrival and time over threshold information. This paper will focus on the design considerations that lead to the ETROC front-end architecture choice, the key design features of the building blocks, the methodology of using the LGAD simulation data to evaluate and optimize the front-end design. The ETROC0 prototype chips have been extensively tested using charge injection and the measured performance agrees well with simulation. The initial beam test results are also presented, with time resolution of around 33 ps observed from the preamplifier waveform analysis and around 41 ps from the discriminator pulses analysis. A subset of ETROC0 chips have also been tested to a total ionizing dose of 100 MRad with X-ray and no performance degradation been observed.

Motivation & Objective

• Develop a low-power, radiation-hard analog front-end for LGAD-based precision timing in the CMS Endcap Timing Layer (ETL) for HL-LHC.
• Achieve sub-50 ps time resolution per hit to enable 30–35 ps track-level timing resolution with two-layer hits.
• Ensure front-end performance is maintained under high radiation levels, including up to 100 MRad total ionizing dose.
• Validate design using LGAD simulation data and charge injection testing before beam tests.
• Establish a foundation for the next-generation ETROC1 chip with integrated TDC and full signal chain evaluation.

Proposed method

• Design a preamplifier and discriminator architecture in 65 nm CMOS to amplify LGAD signals and generate time-of-arrival (TOA) and time-over-threshold (TOT) digital pulses.
• Use LGAD simulation data to model signal response and optimize front-end design for time resolution and signal fidelity.
• Implement a time walk correction using TOT information to improve TOA accuracy.
• Apply charge injection testing to validate timing performance and power consumption across different bias and power modes.
• Conduct beam tests at Fermilab to measure actual time resolution using CFD-based time extraction from preamplifier waveforms.
• Perform TID testing with X-rays up to 100 MRad to assess radiation hardness of the analog front-end.

Experimental results

Research questions

• RQ1 Can a 65 nm CMOS analog front-end achieve 40–50 ps time resolution per hit when interfaced with LGAD sensors in a high-rate, high-radiation environment?
• RQ2 How does the performance of the preamplifier and discriminator stages degrade under increasing radiation doses, and can it maintain specifications after 100 MRad?
• RQ3 To what extent do external spying buffers used in testing affect the measured timing performance, and how does this compare to the true front-end response?
• RQ4 How well does the simulation-based design methodology predict real-world performance in beam tests?
• RQ5 Can the front-end design from ETROC0 be directly reused in the next-generation ETROC1 chip with integrated TDC and full signal chain evaluation?

Key findings

• The ETROC0 prototype achieved a time resolution of 33 ps from preamplifier waveform analysis using constant-fraction timing, indicating strong signal fidelity and low jitter.
• The discriminator output yielded a time resolution of 41 ps after TOT-based time walk correction, slightly below simulation expectations but still within design goals.
• The measured timing performance and power consumption (below 3 mW per channel) closely matched simulation results, validating the design methodology.
• No performance degradation was observed in ETROC0 chips after exposure to 100 MRad of total ionizing dose, confirming radiation tolerance.
• The front-end design from ETROC0 was successfully reused in the next prototype, ETROC1, which integrates a TDC for direct, unspied timing measurement.
• Beam test results confirmed the feasibility of using ETROC0’s front-end for precision timing in the CMS ETL, with further validation planned using ETROC1’s full signal chain.