[Paper Review] The SST Multi-G-Sample/s Switched Capacitor Array Waveform Recorder with Flexible Trigger and Picosecond-Level Timing Accuracy

Stuart Kleinfelder, Edwin Chiem+1 more|arXiv (Cornell University)|Aug 11, 2015

Analog and Mixed-Signal Circuit Design20 references6 citations

TL;DR

This paper presents the SST, a 4-channel, 2 G-samples/s switched capacitor array waveform recorder fabricated in 0.25 µm CMOS, achieving picosecond-level timing accuracy and flexible triggering. It uses synchronous clocking via an LVDS oscillator and supports 6 orders of magnitude in sample rates, with 12-bit resolution, 1.9V input range, and sub-2.5 ps timing jitter across channels after calibration.

ABSTRACT

The design and performance of a multi-G-sample/s fully-synchronous analog transient waveform recorder I.C. ("SST") with fast and flexible trigger capabilities is presented. Containing 4 channels of 256 samples per channel and fabricated in a 0.25 μm CMOS process, it has a 1.9V input range on a 2.5V supply, achieves 12 bits of dynamic range, and uses ~160 mW while operating at 2 G-samples/s and full trigger speeds. With a standard 50 Ohm input source, the SST's analog input bandwidth is ~1.3 GHz within about +/-0.5 dB and reaches a -3 dB bandwidth of 1.5 GHz. The SST's internal sample clocks are generated synchronously via a shift register driven by an external LVDS oscillator, interleaved to double its speed (e.g., a 1 GHz clock yields 2 G-samples/s). It can operate over 6 orders of magnitude in sample rates (2 kHz to 2 GHz). Only three active control lines are necessary for operation: Reset, Start/Stop and Read-Clock. Each of the four channels integrates dual-threshold discrimination of signals with ~1 mV RMS resolution at >600 MHz bandwidth. Comparator results are directly available for simple threshold monitoring and rate control. The High and Low discrimination can also be AND'd over an adjustable window of time in order to exclusively trigger on bipolar impulsive signals. Trigger outputs can be CMOS or low-voltage differential signals, e.g. 1.2V CMOS or positive-ECL (0-0.8V) for low noise. After calibration, the imprecision of timing differences between channels falls in a range of 1.12-2.37 ps sigma at 2 G-samples/s.

Motivation & Objective

• To develop a high-speed, fully-synchronous analog transient waveform recorder for applications requiring precise timing and high dynamic range.
• To enable flexible triggering with dual-threshold discrimination and bipolar impulse detection across multiple channels.
• To achieve sub-2.5 ps timing precision between channels at 2 G-samples/s for ultra-precise waveform sampling.
• To operate over a wide dynamic range of sample rates (2 kHz to 2 GHz) with minimal control complexity.
• To integrate low-power, high-bandwidth signal acquisition with on-chip comparator logic for real-time trigger decisions.

Proposed method

• The SST uses a switched capacitor array architecture with four independent channels, each storing 256 samples.
• Internal sample clocks are generated via a shift register driven by an external LVDS oscillator, with interleaving to achieve 2 G-samples/s from a 1 GHz clock.
• A 3-line control interface (Reset, Start/Stop, Read-Clock) enables full operation with minimal external logic.
• Each channel includes dual-threshold comparators with ~1 mV RMS resolution for signal discrimination and trigger generation.
• Bipolar impulse triggers are implemented by ANDing high and low threshold results over an adjustable time window.
• Timing precision is enhanced through calibration, reducing inter-channel timing jitter to 1.12–2.37 ps sigma at 2 G-samples/s.

Experimental results

Research questions

• RQ1 Can a switched capacitor array achieve sub-2.5 ps inter-channel timing accuracy at 2 G-samples/s?
• RQ2 How effectively can flexible triggering be implemented using on-chip dual-threshold comparators?
• RQ3 What is the achievable bandwidth and dynamic range of a fully-synchronous, multi-channel waveform recorder in a 0.25 µm CMOS process?
• RQ4 To what extent can sample rate be dynamically adjusted across six orders of magnitude while maintaining signal integrity?
• RQ5 How does the integration of on-chip comparator logic impact real-time trigger performance and power efficiency?

Key findings

• The SST achieves a -3 dB analog input bandwidth of 1.5 GHz with a 1.3 GHz bandwidth within ±0.5 dB, using a 50 Ω source.
• The device operates at 2 G-samples/s with 12-bit dynamic range and a 1.9V input range on a 2.5V supply, consuming ~160 mW.
• Inter-channel timing jitter is reduced to 1.12–2.37 ps sigma after calibration at 2 G-samples/s.
• The system supports a 6-decade range of sample rates, from 2 kHz to 2 GHz, using a single external LVDS oscillator.
• Dual-threshold discrimination enables 1 mV RMS resolution for signal detection above 600 MHz bandwidth.
• Trigger outputs can be configured as CMOS or low-voltage differential signals (e.g., 1.2V CMOS or 0–0.8V ECL) for low-noise operation.