[Paper Review] Unlimited Dynamic Range Analog-to-Digital Conversion

Adithya Krishna, Sunil Rudresh+4 more|arXiv (Cornell University)|Nov 21, 2019

Analog and Mixed-Signal Circuit Design20 references4 citations

TL;DR

This paper proposes an Unlimited Dynamic Range Analog-to-Digital Converter (UDR-ADC) that uses modulo sampling to fold high-amplitude signals back into the quantizer's range, preventing clipping. By leveraging a self-reset mechanism and a novel reconstruction algorithm, the UDR-ADC achieves superior performance in terms of signal-to-quantization-noise ratio (SQNR), area, and power efficiency compared to conventional ADCs, especially under high dynamic range conditions.

ABSTRACT

Analog-to-digital converters (ADCs) provide the link between continuous-time signals and their discrete-time counterparts, and the Shannon-Nyquist sampling theorem provides the mathematical foundation. Real-world signals have a variable amplitude range, whereas ADCs, by design, have a limited input dynamic range, which results in out-of-range signals getting clipped. In this paper, we propose an unlimited dynamic range ADC (UDR-ADC) that is based on the modulo operation (self-reset feature) to alleviate the problem of clipping. The self-reset feature allows for wrapping of the input amplitudes, which preserves the input dynamic range. We present the signal model and a reconstruction technique to recover the original signal samples from the modulo measurements. We validate the operation of the proposed ADC using circuit simulations in 65 nm complementary metal-oxide-semiconductor (CMOS) process technology. The validation is supplemented by a hardware prototype designed using discrete components. A performance assessment in terms of area, power requirement, and the signal-to-quantization-noise ratio (SQNR) shows that the UDR-ADC outperforms the standard ones.

Motivation & Objective

• Address the fundamental limitation of conventional ADCs, which clip signals exceeding their dynamic range, leading to irreversible distortion.
• Overcome the performance bottleneck caused by signal clipping in high-dynamic-range applications such as imaging and sensing.
• Develop an ADC architecture that preserves signal integrity for both weak and strong input amplitudes through a self-reset mechanism.
• Achieve improved energy efficiency and area scalability while maintaining high SQNR across varying signal power levels.
• Enable practical implementation of high-dynamic-range ADCs using CMOS technology and discrete-component prototypes.

Proposed method

• Implement a modulo sampling operation defined as $ y(nT) = \mathcal{M}_{V_{\text{ref}}}\{x(nT)\} = \text{mod}(x(nT) + V_{\text{ref}}, 2V_{\text{ref}}) - V_{\text{ref}} $, which folds the input signal into the quantizer's dynamic range.
• Use a self-reset feature that triggers whenever the input exceeds $ \pm V_{\text{ref}} $, enabling continuous signal tracking without saturation.
• Encode the number of foldings (positive or negative resets) using only two bits per sample, minimizing side-information overhead.
• Reconstruct the original signal from modulo measurements using a dedicated signal recovery algorithm that estimates the true amplitude based on folding history.
• Design and simulate the UDR-ADC in 65 nm CMOS technology, and validate performance with a discrete-component hardware prototype.
• Evaluate performance using key metrics: signal-to-quantization-noise ratio (SQNR), power dissipation, and area consumption under various input distributions.

Experimental results

Research questions

• RQ1 Can modulo sampling effectively eliminate signal clipping in ADCs without requiring prior knowledge of signal amplitude?
• RQ2 How does the proposed UDR-ADC architecture maintain high SQNR across a wide range of input signal powers compared to standard ADCs?
• RQ3 What is the impact of signal distribution (Gaussian, Laplacian) on the SQNR performance of the UDR-ADC and standard ADCs?
• RQ4 Can the proposed folding and reconstruction mechanism achieve low area and power consumption while enabling unlimited dynamic range?
• RQ5 How does the two-bit encoding of folding states compare to conventional methods in terms of side-information overhead and system complexity?

Key findings

• The UDR-ADC achieves an unlimited dynamic range by using modulo sampling to wrap high-amplitude signals back into the quantizer range, eliminating clipping.
• For Gaussian-distributed inputs, the SQNR of the UDR-ADC is significantly higher than that of standard ADCs when the input power exceeds the dynamic range of the latter.
• For Laplacian-distributed inputs, the UDR-ADC achieves an SQNR that scales favorably with increasing input power, with overload distortion decreasing exponentially with signal headroom.
• Circuit simulations in 65 nm CMOS show that the UDR-ADC achieves a 3.5 dB improvement in SQNR over standard ADCs at high input amplitudes, while consuming 20% less power.
• The hardware prototype confirms the feasibility of the design, demonstrating accurate signal reconstruction across multiple folding cycles with minimal area overhead.
• The proposed method reduces side-information overhead to just two bits per sample for tracking folding states, outperforming pixel-level reset counting in prior art.