[Paper Review] Early Output Hybrid Input Encoded Asynchronous Full Adder and Relative-Timed Ripple Carry Adder

Padmanabhan Balasubramanian, K. Prasad|arXiv (Cornell University)|Aug 3, 2016

Low-power high-performance VLSI design13 references7 citations

TL;DR

This paper proposes an early-output hybrid input-encoded asynchronous full adder using dual-rail and 1-of-4 delay-insensitive codes, enabling data-dependent forward latency and minimal reverse latency. When used in a ripple carry adder (RCA), it achieves 7.9% lower forward latency and 5.6% smaller area than existing 32-bit RCAs, with a 10.9% improvement in theoretical cycle time, under a small relative-timing assumption for internal carries.

ABSTRACT

This paper presents a new early output hybrid input encoded asynchronous full adder designed using dual-rail and 1-of-4 delay-insensitive data codes. The proposed full adder when cascaded to form a ripple carry adder (RCA) necessitates the use of a small relative-timing assumption with respect to the internal carries, which is independent of the RCA size. The forward latency of the proposed hybrid input encoded full adder based RCA is data-dependent while its reverse latency is the least equaling the propagation delay of just one full adder. Compared to the best of the existing hybrid input encoded full adders based 32-bit RCAs, the proposed early output hybrid input encoded full adder based 32-bit RCA enables respective reductions in forward latency and area by 7.9% and 5.6% whilst dissipating the same average power; in terms of the theoretically computed cycle time, the latter reports a 10.9% reduction compared to the former.

Motivation & Objective

• To design an asynchronous full adder with early output capability to reduce forward latency in ripple carry adders.
• To minimize reverse latency by ensuring it equals only one full adder's propagation delay.
• To reduce area and power consumption while maintaining the same average power dissipation as existing designs.
• To enable scalable, high-performance adder design using hybrid input encoding and delay-insensitive coding.
• To introduce a small relative-timing assumption for internal carries that is independent of RCA size.

Proposed method

• The full adder uses dual-rail and 1-of-4 delay-insensitive data encoding to ensure hazard-free operation in asynchronous circuits.
• It employs hybrid input encoding to represent input signals in a way that supports early output detection.
• The design uses a custom logic structure that allows the sum output to be generated as early as possible based on input transitions.
• The ripple carry adder (RCA) is implemented with a small relative-timing assumption for internal carry signals, decoupling carry propagation from data-dependent delays.
• The circuit is optimized for minimal reverse latency by ensuring the slowest path is limited to a single full adder delay.
• The design is synthesized and evaluated using theoretical cycle time and latency metrics for 32-bit RCA configurations.

Experimental results

Research questions

• RQ1 Can an asynchronous full adder be designed to produce early output while maintaining low reverse latency?
• RQ2 How does hybrid input encoding with dual-rail and 1-of-4 codes affect forward and reverse latency in a ripple carry adder?
• RQ3 What is the impact of introducing a small relative-timing assumption on internal carry signals in terms of area and performance?
• RQ4 To what extent can forward latency and area be reduced compared to existing hybrid input-encoded RCAs?
• RQ5 What is the theoretical cycle time improvement of the proposed RCA over prior designs?

Key findings

• The proposed early-output hybrid input-encoded full adder achieves a 7.9% reduction in forward latency compared to the best existing 32-bit RCA.
• The design reduces area by 5.6% while maintaining the same average power dissipation as prior designs.
• The theoretical cycle time is improved by 10.9% compared to the best existing hybrid input-encoded 32-bit RCA.
• Reverse latency is minimized to just one full adder propagation delay, ensuring minimal worst-case delay.
• The relative-timing assumption for internal carries is small and independent of RCA size, enabling scalable design.
• The use of 1-of-4 and dual-rail encoding ensures hazard-free operation and robustness in asynchronous environments.